Datasheet

Chapter 15 Timer Module (TIM16B8CV1) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 449
Rev 01.24
15.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
Read: Anytime
Write: Anytime.
Module Base + 0x000A
76543210
R
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
W
Reset 0 0 0 00000
Figure 15-16. Timer Control Register 3 (TCTL3)
Module Base + 0x000B
76543210
R
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
W
Reset 0 0 0 00000
Figure 15-17. Timer Control Register 4 (TCTL4)
Table 15-12. TCTL3/TCTL4 Field Descriptions
Field Description
7:0
EDGnB
EDGnA
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Table 15-13. Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)