Datasheet

Chapter 15 Timer Module (TIM16B8CV1) Block Description
444 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
15.3.2.4 Output Compare 7 Data Register (OC7D)
Read: Anytime
Write: Anytime
15.3.2.5 Timer Count Register (TCNT)
Table 15-5. OC7M Field Descriptions
Field Description
7:0
OC7M[7:0]
Output Compare 7 Mask — Setting the OC7Mx (x ranges from 0 to 6) will set the corresponding port to be an
output port when the corresponding TIOSx (x ranges from 0 to 6) bit is set to be an output compare.
Note: A successful channel 7 output compare overrides any channel 6:0 compares. For each OC7M bit that is
set, the output compare action reflects the corresponding OC7D bit.
Module Base + 0x0003
76543210
R
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
W
Reset 0 0 0 00000
Figure 15-9. Output Compare 7 Data Register (OC7D)
Table 15-6. OC7D Field Descriptions
Field Description
7:0
OC7D[7:0]
Output Compare 7 Data — A channel 7 output compare can cause bits in the output compare 7 data register
to transfer to the timer port data register depending on the output compare 7 mask register.
Module Base + 0x0004
15 14 13 12 11 10 9 9
R
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
W
Reset 0 0 0 00000
Figure 15-10. Timer Count Register High (TCNTH)
Module Base + 0x0005
76543210
R
TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
W
Reset 0 0 0 00000
Figure 15-11. Timer Count Register Low (TCNTL)