Datasheet

Chapter 14 Serial Peripheral Interface (SPIV3) Block Description
418 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
14.3.2.2 SPI Control Register 2 (SPICR2)
Read: anytime
Write: anytime; writes to the reserved bits have no effect
Module Base 0x0001
76543210
R000
MODFEN BIDIROE
0
SPISWAI SPC0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 14-4. SPI Control Register 2 (SPICR2)
Table 14-4. SPICR2 Field Descriptions
Field Description
4
MODFEN
Mode Fault Enable Bit — This bit allows the MODF failure being detected. If the SPI is in master mode and
MODFEN is cleared, then the
SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the
SS port pin
configuration refer to Table 14-3. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
0
SS port pin is not used by the SPI
1
SS port pin with MODF feature
3
BIDIROE
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled
1 Output buffer enabled
1
SPISWAI
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode
1 Stop SPI clock generation when in wait mode
0
SPC0
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 14-5. In master
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state
Table 14-5. Bidirectional Pin Configurations
Pin Mode SPC0 BIDIROE MISO MOSI
Master Mode of Operation
Normal 0 X Master In Master Out
Bidirectional 1 0 MISO not used by SPI Master In
1 Master I/O
Slave Mode of Operation
Normal 0 X Slave Out Slave In