Datasheet

Chapter 13 Serial Communications Interface (S12SCIV2) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 403
Rev 01.24
In Figure 13-14 the verification samples RT3 and RT5 determine that the first low detected was noise and
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.
Figure 13-14. Start Bit Search Example 1
In Figure 13-15, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
Figure 13-15. Start Bit Search Example 2
RESET RT CLOCK
RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5
RT10
RT9 RT8
RT14 RT13 RT12 RT11 RT15 RT16
RT1 RT2 RT3
SAMPLES
RT CLOCK
RT CLOCK COUNT
START BIT
Rx Input Signal
110111100000
LSB
0 0
RESET RT CLOCK
RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8
RT11 RT10
RT9
RT14 RT13 RT12
RT2 RT1
RT16 RT15
RT3 RT4 RT5 RT6 RT7
SAMPLES
RT CLOCK
RT CLOCK COUNT
ACTUAL START BIT
Rx Input Signal
1111110000
LSB
00
PERCEIVED START BIT