Datasheet

Chapter 13 Serial Communications Interface (S12SCIV2) Block Description
402 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 13-12 summarizes the results of the data bit samples.
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit (logic 0).
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-13
summarizes the results of the stop bit samples.
Table 13-13. Stop Bit Recovery
100 Yes 1
101 No 0
110 No 0
111 No 0
Table 13-12. Data Bit Recovery
RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag
000 0 0
001 0 1
010 0 1
011 1 1
100 0 1
101 1 1
110 1 1
111 1 0
RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag
000 1 0
001 1 1
010 1 1
011 0 1
100 1 1
101 0 1
110 0 1
111 0 0
Table 13-11. Start Bit Verification
RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag