Datasheet

Chapter 13 Serial Communications Interface (S12SCIV2) Block Description
400 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current frame shifts out through the Tx output signal. Setting TE
after the stop bit appears on Tx output signal causes data previously written
to the SCI data register to be lost. Toggle the TE bit for a queued idle
character while the TDRE flag is set and immediately before writing the
next byte to the SCI data register.
NOTE
If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TXD pin
13.4.4 Receiver
Figure 13-12. SCI Receiver Block Diagram
13.4.4.1 Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
ALL ONES
M
WAKE
ILT
PE
PT
RE
H876543210L
11-BIT RECEIVE SHIFT REGISTER STOP START
DATA
WAKEUP
PARITY
CHECKING
MSB
SCI DATA REGISTER
R8
RIE
ILIE
RWU
RDRF
OR
NF
FE
PE
INTERNAL
BUS
BUS
IDLE INTERRUPT REQUEST
RDRF/OR INTERRUPT REQUEST
SBR12–SBR0
BAUD DIVIDER
LOOP
RSRC
FROM TXD
CLOCK
IDLE
RAF
RECOVERY
CONTROL
LOGIC
LOOPS
RXD