Datasheet

Chapter 13 Serial Communications Interface (S12SCIV2) Block Description
386 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
13.3 Memory Map and Registers
This section provides a detailed description of all memory and registers.
13.3.1 Module Memory Map
The memory map for the SCI module is given below in Figure 13-2. The Address listed for each register
is the address offset. The total address for each register is the sum of the base address for the SCI module
and the address offset for each register.
13.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Writes to a reserved register location do not have any effect and
reads of these locations return a zero. Details of register bit and field function follow the register diagrams,
in bit order.
Address Name Bit 7 65432 1Bit 0
0x0000 SCIBDH
R0 0 0
SBR12 SBR11 SBR10 SBR9 SBR8
W
0x0001 SCIBDL
R
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W
0x0002 SCICR1
R
LOOPS SCISWAI RSRC M WAKE ILT PE PT
W
0x0003 SCICR2
R
TIE TCIE RIE ILIE TE RE RWU SBK
W
0x0004 SCISR1
R TDRE TC RDRF IDLE OR NF FE PF
W
0x0005 SCISR2
R0 0000
BRK13 TXDIR
RAF
W
0x0006 SCIDRH
RR8
T8
0000 0 0
W
0x0007 SCIDRL
RR7 R6R5R4R3R2 R1 R0
WT7 T6T5T4T3T2 T1 T0
= Unimplemented or Reserved
Figure 13-2. SCI Register Summary