Datasheet

Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description

366 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor

Rev 01.24

• The channel is disabled

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some

variation in between. If the channel is not enabled, then writes to the period register will go directly to the

latches as well as the buffer.

NOTE

Reads of this register return the most recent value written. Reads do not

necessarily return the value of the currently active period due to the double

buffering scheme.

Reference Section 12.4.2.3, “PWM Period and Duty,” for more information.

To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,

or SB) and multiply it by the value in the period register for that channel:

• Left aligned output (CAEx = 0)

• PWMx period = channel clock period * PWMPERx center aligned output (CAEx = 1)

• PWMx period = channel clock period * (2 * PWMPERx)

For boundary case programming values, please refer to Section 12.4.2.8, “PWM Boundary Cases.”

Module Base + 0x0012

76543210

Bit 7 6 5 4321Bit 0

Reset 0 0 0 00000

Figure 12-21. PWM Channel Period Registers (PWMPER0)

Module Base + 0x0013

76543210

Bit 7 6 5 4321Bit 0

Reset 0 0 0 00000

Figure 12-22. PWM Channel Period Registers (PWMPER1)

Module Base + 0x0014

76543210

Bit 7 6 5 4321Bit 0

Reset 0 0 0 00000

Figure 12-23. PWM Channel Period Registers (PWMPER2)