Datasheet

Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 365
Rev 01.24
Read: anytime
Write: anytime (any value written causes PWM counter to be reset to 0x0000).
12.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
• The effective period ends
• The counter is written (counter resets to 0x0000)
Module Base + 0x000E
76543210
R Bit 7 6 5 4321Bit 0
W00000000
Reset 0 0 0 00000
Figure 12-17. PWM Channel Counter Registers (PWMCNT2)
Module Base + 0x000F
76543210
R Bit 7 6 5 4321Bit 0
W00000000
Reset 0 0 0 00000
Figure 12-18. PWM Channel Counter Registers (PWMCNT3)
Module Base + 0x00010
76543210
R Bit 7 6 5 4321Bit 0
W00000000
Reset 0 0 0 00000
Figure 12-19. PWM Channel Counter Registers (PWMCNT4)
Module Base + 0x00011
76543210
R Bit 7 6 5 4321Bit 0
W00000000
Reset 0 0 0 00000
Figure 12-20. PWM Channel Counter Registers (PWMCNT5)