Datasheet

Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
358 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
Read: anytime
Write: anytime
NOTE
Write these bits only when the corresponding channel is disabled.
12.3.2.6 PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
Module Base + 0x0004
76543210
R0 0
CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 12-7. PWM Center Align Enable Register (PWMCAE)
Table 12-8. PWMCAE Field Descriptions
Field Description
5
CAE5
Center Aligned Output Mode on Channel 5
0 Channel 5 operates in left aligned output mode.
1 Channel 5 operates in center aligned output mode.
4
CAE4
Center Aligned Output Mode on Channel 4
0 Channel 4 operates in left aligned output mode.
1 Channel 4 operates in center aligned output mode.
3
CAE3
Center Aligned Output Mode on Channel 3
1 Channel 3 operates in left aligned output mode.
1 Channel 3 operates in center aligned output mode.
2
CAE2
Center Aligned Output Mode on Channel 2
0 Channel 2 operates in left aligned output mode.
1 Channel 2 operates in center aligned output mode.
1
CAE1
Center Aligned Output Mode on Channel 1
0 Channel 1 operates in left aligned output mode.
1 Channel 1 operates in center aligned output mode.
0
CAE0
Center Aligned Output Mode on Channel 0
0 Channel 0 operates in left aligned output mode.
1 Channel 0 operates in center aligned output mode.