Datasheet

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
320 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
10.3.3.2 Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
The number of bytes to be transmitted or received is determined by the data length code in the
corresponding DLR register.
Module Base + 0x00X3
76543210
R
W
Reset: xxxxxxxx
= Unused; always read ‘x’
Figure 10-32. Identifier Register 3 — Standard Mapping
Module Base + 0x0004 (DSR0)
0x0005 (DSR1)
0x0006 (DSR2)
0x0007 (DSR3)
0x0008 (DSR4)
0x0009 (DSR5)
0x000A (DSR6)
0x000B (DSR7)
76543210
R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
Reset: xxxxxxxx
Figure 10-33. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
Table 10-30. DSR0–DSR7 Register Field Descriptions
Field Description
7:0
DB[7:0]
Data bits 7:0