Datasheet

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 313
Rev 01.24
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Module Base + 0x001C (CANIDMR4)
0x001D (CANIDMR5)
0x001E (CANIDMR6)
0x001F (CANIDMR7)
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
Figure 10-22. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
Table 10-22. CANIDMR4–CANIDMR7 Register Field Descriptions
Field Description
7:0
AM[7:0]
Acceptance Mask Bits If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit