Datasheet

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
292 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
10.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
10.3.2.1 MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
0x0010–0x0013
CANIDAR0–3
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x0014–0x0017
CANIDMRx
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0018–0x001B
CANIDAR4–7
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
0x001C–0x001F
CANIDMR4–7
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
0x0020–0x002F
CANRXFG
R
See Section 10.3.3, “Programmer’s Model of Message Storage”
W
0x0030–0x003F
CANTXFG
R
See Section 10.3.3, “Programmer’s Model of Message Storage”
W
Module Base + 0x0000
76543210
R
RXFRM
RXACT
CSWAI
SYNCH
TIME WUPE SLPRQ INITRQ
W
Reset: 00000001
= Unimplemented
Figure 10-4. MSCAN Control Register 0 (CANCTL0)
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved u = Unaffected
Figure 10-3. MSCAN Register Summary (continued)