Datasheet

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 283
Rev 01.24
Definition.” All reset sources are listed in Table 9-13. Refer to the device overview chapter for related
vector addresses and priorities.
The reset sequence is initiated by any of the following events:
• Low level is detected at the
RESET pin (external reset).
• Power on is detected.
• Low voltage is detected.
• COP watchdog times out.
• Clock monitor failure is detected and self-clock mode was disabled (SCME = 0).
Upon detection of any reset event, an internal circuit drives the
RESET pin low for 128 SYSCLK cycles
(see Figure 9-25). Because entry into reset is asynchronous it does not require a running SYSCLK.
However, the internal reset circuit of the CRGV4 cannot sequence out of current reset condition without a
running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional
SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK cycles the
RESET pin is released. The reset generator of the CRGV4 waits for additional 64 SYSCLK cycles and
then samples the RESET pin to determine the originating source. Table 9-14 shows which vector will be
fetched.
NOTE
External circuitry connected to the
RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic 1 within 64 SYSCLK cycles after the low drive is released.
Table 9-13. Reset Summary
Reset Source Local Enable
Power-on Reset None
Low Voltage Reset None
External Reset None
Clock Monitor Reset PLLCTL (CME=1, SCME=0)
COP Watchdog Reset COPCTL (CR[2:0] nonzero)
Table 9-14. Reset Vector Selection
Sampled RESET Pin
(64 Cycles After
Release)
Clock Monitor
Reset Pending
COP Reset
Pending
Vector Fetch
1 0 0 POR / LVR / External Reset
1 1 X Clock Monitor Reset
1 0 1 COP Reset
0 X X POR / LVR / External Reset
with rise of
RESET pin