Datasheet

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 271
Rev 01.24
The sequence for clock quality check is shown in Figure 9-20.
Figure 9-20. Sequence for Clock Quality Check
NOTE
Remember that in parallel to additional actions caused by self-clock mode
or clock monitor reset
1
handling the clock quality checker continues to
check the OSCCLK signal.
NOTE
The clock quality checker enables the PLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running PLL (f
SCM
) and an active VREG
during pseudo-stop mode or wait mode
1. A Clock Monitor Reset will always set the SCME bit to logical’1’
check window
osc ok
?
SCM
active?
Switch to OSCCLK
Exit SCM
Clock OK
num=0
num<50
?
num=num+1
yes
no
yes
SCME=1
?
no
Enter SCM
SCM
active?
yes
Clock Monitor Reset
no
yes
no
num=50
yes
no
POR exit full stop
CM fail
LVR