Datasheet

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 265
Rev 01.24
9.3.2.10 Reserved Register (FORBYP)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
modes can alter the CRG’s functionality.
Read: always read 0x0000 except in special modes
Write: only in special modes
9.3.2.11 Reserved Register (CTCTL)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special test
modes can alter the CRG’s functionality.
Read: always read 0x0080 except in special modes
Write: only in special modes
Module Base + 0x0009
76543210
R00000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 9-13. Reserved Register (FORBYP)
Module Base + 0x000A
76543210
R00000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 9-14. Reserved Register (CTCTL)