Datasheet

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 257
Rev 01.24
9.3.2.2 CRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
Read: anytime
Write: anytime except when PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit and the track detector
bit.
9.3.2.3 Reserved Register (CTFLG)
This register is reserved for factory testing of the CRGV4 module and is not available in normal modes.
Read: always reads 0x0000 in normal modes
Write: unimplemented in normal modes
NOTE
Writing to this register when in special mode can alter the CRGV4
functionality.
Module Base + 0x0001
76543210
R0000
REFDV3 REFDV2 REFDV1 REFDV0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 9-5. CRG Reference Divider Register (REFDV)
Module Base + 0x0002
76543210
R00000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 9-6. CRG Reserved Register (CTFLG)