Datasheet

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 255
Rev 01.24
NOTE
Register address = base address + address offset, where the base address is
defined at the MCU level and the address offset is defined at the module
level.
9.3.2 Register Descriptions
This section describes in address order all the CRGV4 registers and their individual bits.
Register
Name
Bit 7 654321Bit 0
0x0000
SYNR
R0 0
SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
W
0x0001
REFDV
R0000
REFDV3 REFDV2 REFDV1 REFDV0
W
0x0002
CTFLG
R00000000
W
0x0003
CRGFLG
R
RTIF PORF LVRF LOCKIF
LOCK TRACK
SCMIF
SCM
W
0x0004
CRGINT
R
RTIE
00
LOCKIE
00
SCMIE
0
W
0x0005
CLKSEL
R
PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
W
0x0006
PLLCTL
R
CME PLLON AUTO ACQ
0
PRE PCE SCME
W
0x0007
RTICTL
R0
RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
0x0008
COPCTL
R
WCOP RSBCK
000
CR2 CR1 CR0
W
0x0009
FORBYP
R00000000
W
0x000A
CTCTL
R00000000
W
= Unimplemented or Reserved
Figure 9-3. CRG Register Summary