Datasheet

Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
242 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
8.3.2.11 ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
Module Base + 0x000D
76543210
R
IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0
W
Reset 0 0 0 00000
Figure 8-13. ATD Input Enable Register (ATDDIEN)
Table 8-17. ATDDIEN Field Descriptions
Field Description
7–0
IEN[7:0]
ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from
the analog input pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.