Datasheet

Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
224 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
8.1.2.2 MCU Operating Modes
• Stop Mode
Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power
standby mode. This aborts any conversion sequence in progress. During recovery from stop mode,
there must be a minimum delay for the stop recovery time, t
SR
, before initiating a new ATD
conversion sequence.
• Wait Mode
Entering wait mode the ATD conversion either continues or aborts for low power depending on the
logical value of the AWAIT bit.
• Freeze Mode
In freeze mode the ATD10B8C will behave according to the logical values of the FRZ1 and FRZ0
bits. This is useful for debugging and emulation.
8.1.3 Block Diagram
Figure 8-1 is a block diagram of the ATD.
Figure 8-1. ATD10B8C Block Diagram
V
RL
AN0 / PAD0
ATD10B8C
PORT AD DATA REGISTER
ANALOG
MUX
MODE AND TIMING CONTROL
SUCCESSIVE
APPROXIMATION
REGISTER (SAR)
RESULTS
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
AND DAC
AN7 / PAD7
AN6 / PAD6
AN5 / PAD5
AN4 / PAD4
AN3 / PAD3
AN2 / PAD2
AN1 / PAD1
SAMPLE & HOLD
1
1
V
RH
V
SSA
V
DDA
CONVERSION
COMPLETE INTERRUPT
+
–
COMPARATOR
CLOCK
PRESCALER
BUS CLOCK
ATD CLOCK
ATD INPUT ENABLE REGISTER