Datasheet

Chapter 7 Debug Module (DBGV1) Block Description

Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 211

Rev 01.24

7.3.2.11 Debug Comparator B Extended Register (DBGCBX)

7.3.2.12 Debug Comparator B Register (DBGCB)

Module Base + 0x002D

76543210

PAGSEL EXTCMP

Reset 0 0 0 00000

Figure 7-19. Debug Comparator B Extended Register (DBGCBX)

Table 7-22. DBGCBX Field Descriptions

Field Description

7:6

PAGSEL

Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Ta bl e 7 -

11.

DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and

11 will be interpreted as values of 00 and 01, respectively.)

In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address

is in the FLASH/ROM memory space.

5:0

EXTCMP

Comparator B Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown

in Table 7-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see Table 7-20.

Module Base + 0x002E

Starting address location affected by INITRG register setting.

15 14 13 12 11 10 9 8

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Reset 0 0 0 00000

Figure 7-20. Debug Comparator B Register High (DBGCBH)