Datasheet

Chapter 7 Debug Module (DBGV1) Block Description
204 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
7.3.2.6 Debug Comparator C Register (DBGCC)
DBGCXX DBGCXH[15:12]
PAGSEL EXTCMP
BIT 15 BIT 14 BIT 13 BIT 12
76
0
5
0
4
3 2 1 BIT 0
SEE NOTE 1
PORTK/XAB
XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14
PPAGE
PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
SEE NOTE 2
NOTES:
1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 7-11.
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
Figure 7-10. Comparator C Extended Comparison in BKP/DBG Mode
Module Base + 0x0026
Starting address location affected by INITRG register setting.
15 14 13 12 11 10 9 8
R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 7-11. Debug Comparator C Register High (DBGCCH)
Module Base + 0x0027
Starting address location affected by INITRG register setting.
76543210
R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 7-12. Debug Comparator C Register Low (DBGCCL)
BKP/DBG MODE