Datasheet

Chapter 7 Debug Module (DBGV1) Block Description

Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 201

Rev 01.24

7.3.2.3 Debug Trace Buffer Register (DBGTB)

Module Base + 0x0022

Starting address location affected by INITRG register setting.

15 14 13 12 11 10 9 8

R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Reset u u u uuuuu

= Unimplemented or Reserved

Figure 7-6. Debug Trace Buffer Register High (DBGTBH)

Module Base + 0x0023

Starting address location affected by INITRG register setting.

76543210

R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset u u u uuuuu

= Unimplemented or Reserved

Figure 7-7. Debug Trace Buffer Register Low (DBGTBL)

Table 7-7. DBGTB Field Descriptions

Field Description

15:0 Trace Buffer Data Bits — The trace buffer data bits contain the data of the trace buffer. This register can be read

only as a word read. Any byte reads or misaligned access of these registers will return 0 and will not cause the

trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the

debugger is armed. In addition, this register may appear to contain incorrect data if it is not read with the same

capture mode bit settings as when the trace buffer data was recorded (See Section 7.4.2.9, “Reading Data from

Trace Buffer”). Because reads will reﬂect the contents of the trace buffer RAM, the reset state is undeﬁned.