Datasheet

Chapter 7 Debug Module (DBGV1) Block Description
196 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
7.3 Memory Map and Register Definition
A summary of the registers associated with the DBG sub-block is shown in Figure 7-3. Detailed
descriptions of the registers and bits are given in the subsections that follow.
7.3.1 Module Memory Map
7.3.2 Register Descriptions
This section consists of the DBG register descriptions in address order. Most of the register bits can be
written to in either BKP or DBG mode, although they may not have any effect in one of the modes.
However, the only bits in the DBG module that can be written while the debugger is armed (ARM = 1) are
DBGEN and ARM
Table 7-2. DBGV1 Memory Map
Address
Offset
Use Access
0x0020 Debug Control Register (DBGC1) R/W
0x0021 Debug Status and Control Register (DBGSC) R/W
0x0022 Debug Trace Buffer Register High (DBGTBH) R
0x0023 Debug Trace Buffer Register Low (DBGTBL) R
0x0024 Debug Count Register (DBGCNT) R
0x0025 Debug Comparator C Extended Register (DBGCCX) R/W
0x0026 Debug Comparator C Register High (DBGCCH) R/W
0x0027 Debug Comparator C Register Low (DBGCCL) R/W
0x0028 Debug Control Register 2 (DBGC2) / (BKPCT0) R/W
0x0029 Debug Control Register 3 (DBGC3) / (BKPCT1) R/W
0x002A Debug Comparator A Extended Register (DBGCAX) / (/BKP0X) R/W
0x002B Debug Comparator A Register High (DBGCAH) / (BKP0H) R/W
0x002C Debug Comparator A Register Low (DBGCAL) / (BKP0L) R/W
0x002D Debug Comparator B Extended Register (DBGCBX) / (BKP1X) R/W
0x002E Debug Comparator B Register High (DBGCBH) / (BKP1H) R/W
0x002F Debug Comparator B Register Low (DBGCBL) / (BKP1L) R/W
Name
(1)
Bit 7 6 5 4 3 2 1 Bit 0
0x0020
DBGC1
R
DBGEN ARM TRGSEL BEGIN DBGBRK
0
CAPMOD
W
0x0021
DBGSC
RAF BF CF 0
TRG
W
= Unimplemented or Reserved
Figure 7-3. DBG Register Summary