Datasheet

Chapter 7 Debug Module (DBGV1) Block Description
194 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
Figure 7-1. DBG Block Diagram in BKP Mode
COMPARATOR
COMPARE BLOCK
REGISTER BLOCK
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
EXPANSION ADDRESSES
EXPANSION ADDRESSES
ADDRESS HIGH
ADDRESS LOW
DATA HIGH
DATA LOW
ADDRESS HIGH
ADDRESS LOW
COMPARATOR
COMPARATOR
READ DATA HIGH
READ DATA LOW
. . . . . .
. . . . . .
CLOCKS AND BKP CONTROL
CONTROL SIGNALS SIGNALS
CONTROL BLOCK
BREAKPOINT MODES
AND GENERATION OF SWI,
FORCE BDM, AND TAGS
EXPANSION ADDRESS
ADDRESS
WRITE DATA
READ DATA
READ/WRITE
CONTROL
CONTROL BITS
CONTROL SIGNALS
RESULTS SIGNALS
BKP0H
BKP0L
BKP0X
BKPCT0
BKP1X
BKPCT1
BKP1L
BKP1H
WRITE
BKP READ
DATA BUS
DATA BUS
DATA/ADDRESS
HIGH MUX
DATA/ADDRESS
LOW MUX