Datasheet

Chapter 6 Background Debug Module (BDMV4) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 173
Rev 01.24
6.3.2.2 BDM CCR Holding Register (BDMCCR)
Read: All modes
Write: All modes
NOTE
When BDM is made active, the CPU stores the value of the CCR register in
the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR
register.
When entering background debug mode, the BDM CCR holding register is used to save the contents of the
condition code register of the user’s program. It is also used for temporary storage in the standard BDM
firmware mode. The BDM CCR holding register can be written to modify the CCR value.
6.3.2.3 BDM Internal Register Position Register (BDMINR)
Read: All modes
Write: Never
0xFF06
76543210
R
CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
W
Reset 0 0 0 00000
Figure 6-4. BDM CCR Holding Register (BDMCCR)
0xFF07
76543210
R 0 REG14 REG13 REG12 REG11 0 0 0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 6-5. BDM Internal Register Position (BDMINR)
Table 6-4. BDMINR Field Descriptions
Field Description
6:3
REG[14:11]
Internal Register Map Position — These four bits show the state of the upper five bits of the base address for
the system’s relocatable register block. BDMINR is a shadow of the INITRG register which maps the register
block to any 2K byte space within the first 32K bytes of the 64K byte address space.