Datasheet

Chapter 6 Background Debug Module (BDMV4) Block Description
168 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
6.3 Memory Map and Register Definition
A summary of the registers associated with the BDM is shown in Figure 6-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
6.3.1 Module Memory Map
Table 6-1. INT Memory Map
Register
Address
Use Access
0xFF00 Reserved
0xFF01 BDM Status Register (BDMSTS) R/W
0xFF02–
0xFF05
Reserved
0xFF06 BDM CCR Holding Register (BDMCCR) R/W
0xFF07 BDM Internal Register Position (BDMINR) R
0xFF08–
0xFF0B
Reserved