Datasheet

Chapter 5 Interrupt (INTV1) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 163
Rev 01.24
5.6.3 Interrupt Priority Decoder
The priority decoder evaluates all interrupts pending and determines their validity and priority. When the
CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt
request. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority
interrupt request could override the original exception that caused the CPU to request the vector. In this
case, the CPU will receive the highest priority vector and the system will process this exception instead of
the original request.
NOTE
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not be processed.
If for any reason the interrupt source is unknown (e.g., an interrupt request becomes inactive after the
interrupt has been recognized but prior to the vector request), the vector address will default to that of the
last valid interrupt that existed during the particular interrupt sequence. If the CPU requests an interrupt
vector when there has never been a pending interrupt request, the INT will provide the software interrupt
(SWI) vector address.
5.7 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request
by the CPU is shown in Table 5-5.
Table 5-5. Exception Vector Map and Priority
Vector Address Source
0xFFFE–0xFFFF System reset
0xFFFC–0xFFFD Crystal monitor reset
0xFFFA–0xFFFB COP reset
0xFFF8–0xFFF9 Unimplemented opcode trap
0xFFF6–0xFFF7 Software interrupt instruction (SWI) or BDM vector request
0xFFF4–0xFFF5
XIRQ signal
0xFFF2–0xFFF3
IRQ signal
0xFFF0–0xFF00 Device-specific I-bit maskable interrupt sources (priority in descending order)