Datasheet

Chapter 5 Interrupt (INTV1) Block Description
160 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
5.3.2.2 Interrupt Test Registers
Read: Only in special modes. Reads will return either the state of the interrupt inputs of the interrupt sub-
block (WRTINT = 0) or the values written into the TEST registers (WRTINT = 1). Reads will always
return 0s in normal modes.
Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1.
Table 5-2. ITCR Field Descriptions
Field Description
4
WRTINT
Write to the Interrupt Test Registers
Read: anytime
Write: only in special modes and with I-bit mask and X-bit mask set.
0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs.
1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers
instead.
Note: Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten.
3:0
ADR[3:0]
Test Register Select Bits
Read: anytime
Write: anytime
These bits determine which test register is selected on a read or write. The hexadecimal value written here will
be the same as the upper nibble of the lower byte of the vector selects. That is, an “F” written into ADR[3:0] will
select vectors 0xFFFE–0xFFF0 while a “7” written to ADR[3:0] will select vectors 0xFF7E–0xFF70.
Module Base + 0x0016
Starting address location affected by INITRG register setting.
76543210
R
INTE INTC INTA INT8 INT6 INT4 INT2 INT0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 5-3. Interrupt TEST Registers (ITEST)