Datasheet
Chapter 5 Interrupt (INTV1) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 159
Rev 01.24
5.2 External Signal Description
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive
direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the
IRQ and
XIRQ pin data.
5.3 Memory Map and Register Deļ¬nition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
5.3.1 Module Memory Map
5.3.2 Register Descriptions
5.3.2.1 Interrupt Test Control Register
Read: See individual bit descriptions
Write: See individual bit descriptions
Table 5-1. INT Memory Map
Address
Offset
Use Access
0x0015 Interrupt Test Control Register (ITCR) R/W
0x0016 Interrupt Test Registers (ITEST) R/W
0x001F Highest Priority Interrupt (Optional) (HPRIO) R/W
Module Base + 0x0015
Starting address location affected by INITRG register setting.
76543210
R000
WRTINT ADR3 ADR2 ADR1 ADR0
W
Reset 0 0 0 01111
= Unimplemented or Reserved
Figure 5-2. Interrupt Test Control Register (ITCR)