Datasheet

Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 157
Rev 01.24
Chapter 5
Interrupt (INTV1) Block Description
5.1 Introduction
This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform.
A block diagram of the interrupt sub-block is shown in Figure 5-1.
Figure 5-1. INTV1 Block Diagram
HPRIO (OPTIONAL)
INT
PRIORITY DECODER
VECTOR REQUEST
INTERRUPTS
RESET FLAGS
WRITE DATA BUS
HPRIO VECTOR
XMASK
IMASK
QUALIFIED
INTERRUPT INPUT REGISTERS
INTERRUPTS
AND CONTROL REGISTERS
HIGHEST PRIORITY
I-INTERRUPT
READ DATA BUS
WAKEUP
VECTOR ADDRESS
INTERRUPT PENDING