Datasheet

Chapter 4 Multiplexed External Bus Interface (MEBIV3)
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 135
Rev 01.24
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines
D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in single-
chip mode, these pins can be used as general-purpose I/O. Data direction register A (DDRA) determines
the primary direction of each pin. DDRA also determines the source of data for a read of PORTA.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
NOTE
To ensure that you read the value present on the PORTA pins, always wait
at least one cycle after writing to the DDRA register before reading from the
PORTA register.
4.3.2.2 Port B Data Register (PORTB)
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Port B bits 7 through 0 are associated with address lines A7 through A0 respectively and data lines D7
through D0 respectively. When this port is not used for external addresses, such as in single-chip mode,
these pins can be used as general-purpose I/O. Data direction register B (DDRB) determines the primary
direction of each pin. DDRB also determines the source of data for a read of PORTB.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
NOTE
To ensure that you read the value present on the PORTB pins, always wait
at least one cycle after writing to the DDRB register before reading from the
PORTB register.
Module Base + 0x0001
Starting address location affected by INITRG register setting.
76543210
R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0
Single Chip PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Expanded Wide,
Emulation Narrow with
IVIS, and Peripheral
AB/DB7 AB/DB6 AB/DB5 AB/DB4 AB/DB3 AB/DB2 AB/DB1 AB/DB0
Expanded Narrow AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
Figure 4-3. Port A Data Register (PORTB)