Datasheet

Chapter 4 Multiplexed External Bus Interface (MEBIV3)
134 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
4.3.1 Module Memory Map
4.3.2 Register Descriptions
4.3.2.1 Port A Data Register (PORTA)
Table 4-2. MEBI Memory Map
Address
Offset
Use Access
0x0000 Port A Data Register (PORTA) R/W
0x0001 Port B Data Register (PORTB) R/W
0x0002 Data Direction Register A (DDRA) R/W
0x0003 Data Direction Register B (DDRB) R/W
0x0004 Reserved R
0x0005 Reserved R
0x0006 Reserved R
0x0007 Reserved R
0x0008 Port E Data Register (PORTE) R/W
0x0009 Data Direction Register E (DDRE) R/W
0x000A Port E Assignment Register (PEAR) R/W
0x000B Mode Register (MODE) R/W
0x000C Pull Control Register (PUCR) R/W
0x000D Reduced Drive Register (RDRIV) R/W
0x000E External Bus Interface Control Register (EBICTL) R/W
0x000F Reserved R
0x001E IRQ Control Register (IRQCR) R/W
0x00032 Port K Data Register (PORTK) R/W
0x00033 Data Direction Register K (DDRK) R/W
Module Base + 0x0000
Starting address location affected by INITRG register setting.
76543210
R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0
Single Chip PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Expanded Wide,
Emulation Narrow with
IVIS, and Peripheral
AB/DB15 AB/DB14 AB/DB13 AB/DB12 AB/DB11 AB/DB10 AB/DB9 AB/DB8
Expanded Narrow AB15 and
DB15/DB7
AB14 and
DB14/DB6
AB13 and
DB13/DB5
AB12 and
DB12/DB4
AB11 and
DB11/DB3
AB10 and
DB10/DB2
AB9 and
DB9/DB1
AB8 and
DB8/DB0
Figure 4-2. Port A Data Register (PORTA)