Datasheet

Chapter 4 Multiplexed External Bus Interface (MEBIV3)
132 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
.
Table 4-1. External System Pins Associated With MEBI
Pin Name Pin Functions Description
BKGD/MODC/
TAGHI
MODC At the rising edge on
RESET, the state of this pin is registered into the MODC
bit to set the mode. (This pin always has an internal pullup.)
BKGD Pseudo open-drain communication pin for the single-wire background debug
mode. There is an internal pull-up resistor on this pin.
TAGHI When instruction tagging is on, a 0 at the falling edge of E tags the high half of
the instruction word being read into the instruction queue.
PA7/A15/D15/D7
thru
PA0/A8/D8/D0
PA7–PA0 General-purpose I/O pins, see PORTA and DDRA registers.
A15–A8 High-order address lines multiplexed during ECLK low. Outputs except in
special peripheral mode where they are inputs from an external tester system.
D15–D8 High-order bidirectional data lines multiplexed during ECLK high in expanded
wide modes, special peripheral mode, and visible internal accesses (IVIS = 1)
in emulation expanded narrow mode. Direction of data transfer is generally
indicated by R/
W.
D15/D7
thru
D8/D0
Alternate high-order and low-order bytes of the bidirectional data lines
multiplexed during ECLK high in expanded narrow modes and narrow accesses
in wide modes. Direction of data transfer is generally indicated by R/
W.
PB7/A7/D7
thru
PB0/A0/D0
PB7–PB0 General-purpose I/O pins, see PORTB and DDRB registers.
A7–A0 Low-order address lines multiplexed during ECLK low. Outputs except in
special peripheral mode where they are inputs from an external tester system.
D7–D0 Low-order bidirectional data lines multiplexed during ECLK high in expanded
wide modes, special peripheral mode, and visible internal accesses (with
IVIS = 1) in emulation expanded narrow mode. Direction of data transfer is
generally indicated by R/
W.
PE7/NOACC PE7 General-purpose I/O pin, see PORTE and DDRE registers.
NOACC CPU No Access output. Indicates whether the current cycle is a free cycle. Only
available in expanded modes.
PE6/IPIPE1/
MODB/CLKTO
MODB At the rising edge of
RESET, the state of this pin is registered into the MODB
bit to set the mode.
PE6 General-purpose I/O pin, see PORTE and DDRE registers.
IPIPE1 Instruction pipe status bit 1, enabled by PIPOE bit in PEAR.
CLKTO System clock test output. Only available in special modes. PIPOE = 1 overrides
this function. The enable for this function is in the clock module.
PE5/IPIPE0/MODA MODA At the rising edge on
RESET, the state of this pin is registered into the MODA
bit to set the mode.
PE5 General-purpose I/O pin, see PORTE and DDRE registers.
IPIPE0 Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.