Datasheet

Chapter 3 Module Mapping Control (MMCV4) Block Description
118 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
3.3.2.7 Memory Size Register 0 (MEMSIZ0)
Read: Anytime
Write: Writes have no effect
Reset: Defined at chip integration, see device overview section.
The MEMSIZ0 register reflects the state of the register, EEPROM and RAM memory space configuration
switches at the core boundary which are configured at system integration. This register allows read
visibility to the state of these switches.
Module Base + 0x001C
Starting address location affected by INITRG register setting.
76543210
R REG_SW0 0 EEP_SW1 EEP_SW0 0 RAM_SW2 RAM_SW1 RAM_SW0
W
Reset — — ——————
= Unimplemented or Reserved
Figure 3-9. Memory Size Register 0 (MEMSIZ0)
Table 3-7. MEMSIZ0 Field Descriptions
Field Description
7
REG_SW0
Allocated System Register Space
0 Allocated system register space size is 1K byte
1 Allocated system register space size is 2K byte
5:4
EEP_SW[1:0]
Allocated System EEPROM Memory Space — The allocated system EEPROM memory space size is as
given in Table 3-8.
2
RAM_SW[2:0]
Allocated System RAM Memory Space — The allocated system RAM memory space size is as given in
Table 3-9.
Table 3-8. Allocated EEPROM Memory Space
eep_sw1:eep_sw0 Allocated EEPROM Space
00 0K byte
01 2K bytes
10 4K bytes
11 8K bytes
Table 3-9. Allocated RAM Memory Space
ram_sw2:ram_sw0
Allocated
RAM Space
RAM
Mappable Region
INITRM
Bits Used
RAM Reset
Base Address
(1)
000 2K bytes 2K bytes RAM[15:11] 0x0800
001 4K bytes 4K bytes RAM[15:12] 0x0000
010 6K bytes 8K bytes
(2)
RAM[15:13] 0x0800