Datasheet

Chapter 3 Module Mapping Control (MMCV4) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 117
Rev 01.24
3.3.2.5 Reserved Test Register 0 (MTST0)
Read: Anytime
Write: No effect — this register location is used for internal test purposes.
3.3.2.6 Reserved Test Register 1 (MTST1)
Read: Anytime
Write: No effect — this register location is used for internal test purposes.
Table 3-6. External Stretch Bit Definition
Stretch Bit EXSTR1 Stretch Bit EXSTR0 Number of E Clocks Stretched
00 0
01 1
10 2
11 3
Module Base + 0x0014
Starting address location affected by INITRG register setting.
76543210
R00000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 3-7. Reserved Test Register 0 (MTST0)
Module Base + 0x0017
Starting address location affected by INITRG register setting.
76543210
R00000000
W
Reset 0 0 0 10000
= Unimplemented or Reserved
Figure 3-8. Reserved Test Register 1 (MTST1)