Datasheet
Chapter 2 Port Integration Module (PIM9C32) Block Description
102 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor
Rev 01.24
2.3.2.6.3 Port AD Data Direction Register (DDRAD)
Read: Anytime.
Write: Anytime.
2.3.2.6.4 Port AD Reduced Drive Register (RDRAD)
Read: Anytime.
Write: Anytime.
Module Base + 0x0032
76543210
R
DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0
W
Reset 0 0 0 00000
Figure 2-42. Port AD Data Direction Register (DDRAD)
Table 2-34. DDRAD Field Descriptions
Field Description
7–0
DDRAD[7:0]
Data Direction Port AD — This register configures port pins AD[7:0] as either input or output.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on
PTAD or PTIAD registers, when changing the DDRAD register.
Module Base + 0x0033
76543210
R
RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0
W
Reset 0 0 0 00000
Figure 2-43. Port AD Reduced Drive Register (RDRAD)
Table 2-35. RDRAD Field Descriptions
Field Description
7–0
RDRAD[7:0]
Reduced Drive Port AD — This register configures the drive strength of each port AD output pin as either full
or reduced. If the port is used as input this bit is ignored.
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.