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HCS12

Microcontrollers

freescale.com

MC9S12C Family

MC9S12GC Family

Reference Manual

MC9S12C128

Rev 01.24

05/2010

Summary of content (690 pages)

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MC9S12C Family MC9S12GC Family Reference Manual HCS12 Microcontrollers MC9S12C128 Rev 01.24 05/2010 freescale.
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices. The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the S12 CPU.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) . 17 Chapter 2 Port Integration Module (PIM9C32) . . . . . . . . . . . . . . . . . . . . . 73 Chapter 3 Module Mapping Control (MMCV4) . . . . . . . . . . . . . . . . . . . . 109 Chapter 4 Multiplexed External Bus Interface (MEBIV3) . . . . . . . . . . . . 129 Chapter 5 Interrupt (INTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Chapter 6 Background Debug Module (BDMV4) . . . . . . . . . . . . . . . . . .
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Appendix E Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 4 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.2 2.3 2.4 2.5 2.6 2.7 2.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . .
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4.4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.4.4 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Chapter 5 Interrupt (INTV1) Block Description 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Introduction . . . . . . . . .
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6.4.10 6.4.11 6.4.12 6.4.13 6.4.14 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Serial Communication Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8.4 8.5 8.6 8.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 8.4.1 Analog Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 8.4.2 Digital Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . .
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.1.
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12.2 12.3 12.4 12.5 12.6 12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 External Signal Description . . . . . . . . . . . . . . . . . . . . .
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 14.1.
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15.3 15.4 15.5 15.6 15.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 439 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.6.1 LVI — Low-Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.1.1 Glossary . . . . . . . .
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19.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 19.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 19.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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21.4.2 21.4.3 21.4.4 21.4.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.1 Introduction The MC9S12C-Family / MC9S12GC-Family are 48/52/80 pin Flash-based MCU families, which deliver the power and flexibility of the 16-bit core to a whole new range of cost and space sensitive, general purpose industrial and automotive network applications.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) • • • • • • • 18 Memory options: — 16K or 32Kbyte Flash EEPROM (erasable in 512-byte sectors) 64K, 96K, or 128Kbyte Flash EEPROM (erasable in 1024-byte sectors) — 1K, 2K or 4K Byte RAM Analog-to-digital converters: — One 8-channel module with 10-bit resolution — External conversion trigger capability Available on MC9S12C Family: — One 1M bit per second, CAN 2.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) • • • • 1.1.2 Operating frequency: — 32MHz equivalent to 16MHz bus speed for single chip — 32MHz equivalent to 16MHz bus speed in expanded bus modes — Option of 9S12C Family: 50MHz equivalent to 25MHz bus speed — All 9S12GC Family members allow a 50MHz operating frequency. Internal 2.5V regulator: — Supports an input voltage range from 2.97V to 5.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Block Diagram VDDA VSSA VRH VRL Key Int TEST/VPP PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 PTB DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PTA ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DDRB DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 Multiplexed Wide Bus DDRA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Multiplexed Address/Data Bus Internal Logic 2.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.2 1.2.1 Memory Map and Registers Device Memory Map Table 1-1 shows the device register map after reset. Figure 1-2 through Figure 1-6 illustrate the full device memory map. Table 1-1.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0000 1K Register Space 0x03FF Mappable to any 2K Boundary PAGE MAP 0x0000 0x0400 0x0000 16K Fixed Flash EEPROM 0x3FFF 0x3000 0x4000 0x003D 0x3000 4K Bytes RAM 0x3FFF Mappable to any 4K Boundary 0x4000 16K Fixed Flash EEPROM 0x003E 16K Page Window 8 * 16K Flash EEPROM Pages PPAGE 0x7FFF 0x8000 0x8000 EXT 0xBFFF 0xC000 0xC000 0xFFFF 0xFF00 0xFF00 0xFFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0000 1K Register Space 0x03FF Mappable to any 2K Boundary PAGE MAP 0x0000 0x0400 0x0000 16K Fixed Flash EEPROM 0x3FFF 0x3000 0x4000 0x003D 0x3000 4K Bytes RAM 0x3FFF Mappable to any 4K Boundary 0x4000 16K Fixed Flash EEPROM 0x003E 16K Page Window 6 * 16K Flash EEPROM Pages PPAGE 0x7FFF 0x8000 0x8000 EXT 0xBFFF 0xC000 0xC000 0xFFFF 0xFF00 0xFF00 0xFFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0000 1K Register Space 0x03FF Mappable to any 2K Boundary PAGE MAP 0x0000 0x0400 0x0000 16K Fixed Flash EEPROM 0x3FFF 0x3000 0x4000 0x003D 0x3000 4K Bytes RAM 0x3FFF Mappable to any 4K Boundary 0x4000 16K Fixed Flash EEPROM 0x003E 16K Page Window 4 * 16K Flash EEPROM Pages PPAGE 0x7FFF 0x8000 0x8000 EXT 0xBFFF 0xC000 0xC000 0xFFFF 0xFF00 0xFF00 0xFFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0000 1K Register Space 0x0000 0x0400 0x03FF Mappable to any 2K Boundary 0x3800 0x3800 2K Bytes RAM 0x3FFF Mappable to any 2K Boundary PAGE MAP 0x4000 0x003E 0x8000 0x8000 16K Page Window 2 * 16K Flash EEPROM Pages EXT PPAGE 0xBFFF 0xC000 0xC000 0xFFFF 0xFF00 0xFF00 0xFFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP 0xFFFF 16K Fixed Flash EEPROM 0x003F BDM (If Active) The figure shows a use
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0000 1K Register Space 0x0000 0x0400 0x03FF Mappable to any 2K Boundary 0x3C00 0x3C00 1K Bytes RAM 0x3FFF Mappable to any 2K Boundary PAGE MAP 0x4000 0x8000 0x8000 16K Page Window EXT PPAGE 0xBFFF 0xC000 0xC000 0xFFFF 0xFF00 0xFF00 0xFFFF VECTORS VECTORS VECTORS NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP 0xFFFF 16K Fixed Flash EEPROM 0x003F BDM (If Active) The figure shows a useful map, which is not the map out of
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.2.2 Detailed Register Map The detailed register map of the MC9S12C128 is listed in address order below.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0010–0x0014 Address Name 0x0010 INITRM 0x0011 INITRG 0x0012 INITEE 0x0013 MISC 0x0014 Reserved 0x0015–0x0016 Address Name 0x0015 ITCR 0x0016 ITEST 0x0017–0x0017 Address Name 0x0017 Reserved 0x0018–0x0018 Address Name 0x0018 Reserved 0x0019–0x0019 Address $0019 28 MMC Map 1 of 4 (HCS12 Module Mapping Control) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 6 Bit 5 Bit 4 Bit 3 RAM15 RAM14 RAM
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x001A–0x001B Address Name 0x001A PARTIDH 0x001B PARTIDL 0x001C–0x001D Address Name 0x001C MEMSIZ0 0x001D MEMSIZ1 0x001E–0x001E Address Name 0x001E INTCR 0x001F–0x001F Address 0x001F Miscellaneous Peripherals (Device User Guide) Read: Write: Read: Write: 0x0020–0x002F Address Name 0x0020 DBGC1 0x0021 DBGSC 0x0022 DBGTBH 0x0023 DBGTBL 0x0024 DBGCNT 0x0025 DBGCCX Freescale Semiconductor Bit 6 Bit 5 Bit 4 Bit 3 Bi
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0020–0x002F Address Name 0x0026 DBGCCH 0x0027 DBGCCL 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F DBGC2 BKPCT0 DBGC3 BKPCT1 DBGCAX BKP0X DBGCAH BKP0H DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L 0x0030–0x0031 Address Name 0x0030 PPAGE 0x0031 Reserved 0x0032–0x0033 Address Name 0x0032 PORTK(1) 0x0033 DDRK1 Address Name $0032 Reserved $0033 Reserved DBG (Including BKP) Map 1 of 1 (HCS12 Debug) (continued
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0034–0x003F ep Address Name 0x0034 SYNR 0x0035 REFDV 0x0036 CTFLG TEST ONLY 0x0037 CRGFLG 0x0038 CRGINT 0x0039 CLKSEL 0x003A PLLCTL 0x003B RTICTL 0x003C COPCTL 0x003D FORBYP TEST ONLY 0x003E CTCTL TEST ONLY 0x003F ARMCOP CRG (Clock and Reset Generator) Bit 7 Bit 6 Read: 0 Write: Read: 0 Write: Read: TOUT7 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: CME Write: Read: 0 Write: Read: WCOP Write:
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Address Name 0x0048 TCTL1 0x0049 TCTL2 0x004A TCTL3 0x004B TCTL4 0x004C TIE 0x004D TSCR2 0x004E TFLG1 0x004F TFLG2 0x0050 TC0 (hi) 0x0051 TC0 (lo) 0x0052 TC1 (hi) 0x0053 TC1 (lo) 0x0054 TC2 (hi) 0x0055 TC2 (lo) 0x0056 TC3 (hi) 0x0057 TC3 (lo) 0x0058 TC4 (hi) 0x0059 TC4 (lo) 0x005A TC5 (hi) 0x005B TC5 (lo) 0x005C TC6 (hi) 0x005D TC6 (lo) 0x005E TC7 (hi) 32 Read: Write: Read: Write: Read: Write: Read:
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Address Name 0x005F TC7 (lo) 0x0060 PACTL 0x0061 PAFLG 0x0062 PACNT (hi) 0x0063 PACNT (lo) 0x0064 Reserved 0x0065 Reserved 0x0066 Reserved 0x0067 Reserved 0x0068 Reserved 0x0069 Reserved 0x006A Reserved 0x006B Reserved 0x006C Reserved 0x006D Reserved 0x006E Reserved 0x006F Reserved 0x0070–0x007F Address 0x0070– 0x007F Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Rea
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0080–0x009F Address Name 0x0080 ATDCTL0 0x0081 ATDCTL1 0x0082 ATDCTL2 0x0083 ATDCTL3 0x0084 ATDCTL4 0x0085 ATDCTL5 0x0086 ATDSTAT0 0x0087 Reserved 0x0088 ATDTEST0 0x0089 ATDTEST1 0x008A Reserved 0x008B ATDSTAT1 0x008C Reserved 0x008D ATDDIEN 0x008E Reserved 0x008F PORTAD 0x0090 ATDDR0H 0x0091 ATDDR0L 0x0092 ATDDR1H 0x0093 ATDDR1L 0x0094 ATDDR2H 0x0095 ATDDR2L 34 ATD (Analog-to-Digital Converter 10 B
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0080–0x009F Address Name 0x0096 ATDDR3H 0x0097 ATDDR3L 0x0098 ATDDR4H 0x0099 ATDDR4L 0x009A ATDDR5H 0x009B ATDDR5L 0x009C ATDDR6H 0x009D ATDDR6L 0x009E ATDDR7H 0x009F ATDDR7L 0x00A0–0x00C7 Address Name 0x00A0– 0x00C7 Reserved 0x00C8–0x00CF Address Name 0x00C8 SCIBDH 0x00C9 SCIBDL 0x00CA SCICR1 0x00CB SCICR2 0x00CC SCISR1 Freescale Semiconductor ATD (Analog-to-Digital Converter 10 Bit 8 Channel) (continued)
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x00C8–0x00CF Address Name 0x00CD SCISR2 0x00CE SCIDRH 0x00CF SCIDRL 0x00D0–0x00D7 Address 0x00D0– 0x00D7 Read: Write: Read: Write: Read: Write: Reserved Address Name 0x00D8 SPICR1 0x00D9 SPICR2 0x00DA SPIBR 0x00DB SPISR 0x00DC Reserved 0x00DD SPIDR 0x00DE Reserved 0x00DF Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 0 0 0 0 0 0 R6 T6 R5 T5 Bit 7 Bit 6 0 0 R8 R7 T7 T8 Bit 2 Bit 1 Bit 0 BRK13 TXDIR 0
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x00E0–0x00FF Address Name $00E0 PWME $00E1 PWMPOL $00E2 PWMCLK $00E3 PWMPRCLK $00E4 PWMCAE $00E5 PWMCTL $00E6 PWMTST Test Only $00E7 PWMPRSC $00E8 PWMSCLA $00E9 PWMSCLB $00EA PWMSCNTA $00EB PWMSCNTB $00EC PWMCNT0 $00ED PWMCNT1 $00EE PWMCNT2 $00EF PWMCNT3 $00F0 PWMCNT4 $00F1 PWMCNT5 $00F2 PWMPER0 $00F3 PWMPER1 $00F4 PWMPER2 $00F5 PWMPER3 Freescale Semiconductor PWM (Pulse Width Modulator) Read: Write:
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x00E0–0x00FF Address Name $00F6 PWMPER4 $00F7 PWMPER5 $00F8 PWMDTY0 $00F9 PWMDTY1 $00FA PWMDTY2 $00FB PWMDTY3 $00FC PWMDTY4 $00FD PWMDTY5 $00FE Reserved $00FF Reserved 0x0110–0x013F Address Name 0x0110– 0x003F Reserved 0x0140–0x017F Address Name 0x0140 CANCTL0 0x0141 CANCTL1 0x0142 CANBTR0 0x0143 CANBTR1 0x0144 CANRFLG 0x0145 CANRIER 38 PWM (Pulse Width Modulator) (continued) Read: Write: Read: Write: Read
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0140–0x017F Address CAN (Scalable Controller Area Network — MSCAN)(1) (continued) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 0 TXE2 TXE1 TXE0 Write: Read: 0 0 0 0 0 0x0147 CANTIER TXEIE2 TXEIE1 TXEIE0 Write: Read: 0 0 0 0 0 0x0148 CANTARQ ABTRQ2 ABTRQ1 ABTRQ0 Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0x0149 CANTAAK Write: Read: 0 0 0 0 0 0x014A CANTBSEL TX2 TX1 TX0 Write: Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0 0x01
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Table 1-2.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0180–0x023F Address Name 0x0180– 0x023F Reserved 0x0240–0x027F Address Reserved Read: Write: PTT 0x0241 PTIT 0x0242 DDRT 0x0243 RDRT 0x0244 PERT 0x0245 PPST 0x0246 Reserved 0x0247 MODRR 0x0248 PTS 0x0249 PTIS 0x024A DDRS 0x024B RDRS 0x024C PERS 0x024D PPSS 0x024E WOMS 0x024F Reserved 0x0250 PTM 0x0251 PTIM 0x0252 DDRM Freescale Semiconductor Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0240–0x027F Address Name 0x0253 RDRM 0x0254 PERM 0x0255 PPSM 0x0256 WOMM 0x0257 Reserved 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP 0x025D PPSP 0x025E PIEP 0x025F PIFP 0x0260 Reserved 0x0261 Reserved 0x0262 Reserved 0x0263 Reserved 0x0264 Reserved 0x0265 Reserved 0x0266 Reserved 0x0267 Reserved 0x0268 PTJ 0x0269 PTIJ 42 PIM (Port Interface Module) (Sheet 2 of 3) Read: Write: Read:
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 0x0240–0x027F Address Name 0x026A DDRJ 0x026B RDRJ 0x026C PERJ 0x026D PPSJ 0x026E PIEJ 0x026F PIFJ 0x0270 PTAD 0x0271 PTIAD 0x0272 DDRAD 0x0273 RDRAD 0x0274 PERAD 0x0275 PPSAD 0x02760x027F Reserved 0x0280–0x03FF Address PIM (Port Interface Module) (Sheet 3 of 3) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Rea
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.2.3 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and ox001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID numbers for production mask sets. Table 1-3.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.
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PP5/KWP5/PW5 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PS1/TXD PS0/RXD VSSA 51 50 49 48 47 46 45 44 43 42 41 40 PP4/KWP4/PW4 52 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 39 VRH 2 38 VDDA PW1/IOC1/PT1 3 37 PW2/IOC2/PT2 4 36 PW3/IOC3/PT3 5 35 PAD07/AN07 PAD06/AN06 PAD05/AN05 VDD1 6 34 PAD04/AN04 VSS1 7 33 PAD03/AN03 IOC4/PT4 8 32 PAD02/AN02 IOC5/PT5 9 31 PAD01/AN01 IOC6/PT6 10 30 PAD00/AN00 IOC7/PT7 11 29 PA2
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VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PS1/TXD PS0/RXD VSSA 46 45 44 43 42 41 40 39 38 37 VDDX PW1/IOC1/PT1 47 1 PP5/KWP5/PW5 PW0/IOC0/PT0 48 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) VRH 2 35 VDDA PW2/IOC2/PT2 3 34 PW3/IOC3/PT3 4 33 VDD1 5 32 PAD07/AN07 PAD06/AN06 PAD05/AN05 VSS1 6 31 PAD04/AN04 IOC4/PT4 7 30 PAD03/AN03 IOC5/PT5 8 29 PAD02/AN02 IOC6/PT6 9 28 PAD01/AN01 IOC7/PT7 10 27 PAD00/AN00 MODC/BKGD 11 2
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.3.2 Signal Properties Summary Table 1-5.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Table 1-5.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.3.4 1.3.4.1 Detailed Signal Descriptions EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 1.3.4.2 RESET — External Reset Pin RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.3.4.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins PA7–PA0 are general purpose input or output pins,. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PA[7:1] pins are not available in the 48-pin package version. PA[7:3] are not available in the 52-pin package version. 1.3.4.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins PB7–PB0 are general purpose input or output pins.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) EXTAL CMOS Compatible External Oscillator (VDDPLL Level) MCU XTAL Not Connected Figure 1-13. External Clock Connections (PE7 = 0) 1.3.4.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.3.4.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until enabled. This pin is not available in the 48- / 52-pin package versions. 1.3.4.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. • PP6 = 1 in emulation modes equates to ROMON = 0 (ROM space externally mapped) • PP6 = 0 in expanded modes equates to ROMON = 0 (ROM space externally mapped) 1.3.4.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0] PP[5:0] are general purpose input or output pins, shared with the keypad interrupt function.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.3.4.27 PS[3:2] — Port S I/O Pins [3:2] PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48- / 52-pin package versions. 1.3.4.28 PS1 / TXD — Port S I/O Pin 1 PS1 is a general purpose input or output pin and the transmit pin, TXD, of serial communication interface (SCI). 1.3.4.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.3.5.4 VDDA, VSSA — Power Supply Pins for ATD and VREG VDDA, VSSA are the power supply and ground input pins for the voltage regulator reference and the analog to digital converter. 1.3.5.5 VRH, VRL — ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter. 1.3.5.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.4 System Clock Description The clock and reset generator provides the internal clock signals for the core and all peripheral modules. Figure 1-14 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation. S12_CORE Core Clock Flash RAM TIM ATD PIM EXTAL SCI Bus Clock CRG Oscillator Clock SPI MSCAN Not on 9S12GC XTAL VREG TPM Figure 1-14. Clock Connections 1.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Table 1-7. Mode Selection BKGD = MODC PE6 = MODB PE5 = MODA PP6 = ROMCTL ROMON Bit Mode Description 0 0 0 X 1 Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration. 1.5.2.2 1.5.2.2.1 Operation of the Secured Microcontroller Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 1.5.2.2.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.5.3.3 Wait This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay active. For further power consumption reduction the peripherals can individually turn off their local clocks. 1.5.3.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Table 1-9.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.6.2 Resets Resets are a subset of the interrupts featured in Table 1-9. The different sources capable of generating a system reset are summarized in Table 1-10. When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states. 1.6.2.1 Reset Summary Table Table 1-10. Reset Summary 1.6.2.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Table 1-11. Device Specific Flash PAGE Mapping Device PAGE PAGE Visible with PPAGE Contents MC9S12GC16 3F $01,$03,$05,$07,$09......$35,$37,$39,$3B,$3D,$3F MC9S12C32 MC9S12GC32 3E $00,$02,$04,$06,$08,$0A,$0C,$0E,$10,$12......$2C,$2E,$30,$32,$34,$36,$38,$3A,$3C,$3E 3F $01,$03,$05,$07,$09,$0B,$0D,$0F,$11,$13.....
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.7.4 VREGEN The VREGEN input mentioned in the VREG section is device internal, connected internally to VDDR. 1.7.5 VDD1, VDD2, VSS1, VSS2 In the 80-pin QFP package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2 sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected together internally. VSS1 and VSS2 are connected together internally.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 1.8 Recommended Printed Circuit Board Layout The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins. • Central point of the ground star should be the VSSR pin. • Use low ohmic low inductance connections between VSS1, VSS2, and VSSR.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-15. Recommended PCB Layout (48 LQFP) Colpitts Oscillator 66 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-16. Recommended PCB Layout (52 LQFP) Colpitts Oscillator Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-17. Recommended PCB Layout (80 QFP) Colpitts Oscillator 68 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-18. Recommended PCB Layout for 48 LQFP Pierce Oscillator Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-19. Recommended PCB Layout for 52 LQFP Pierce Oscillator 70 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-20. Recommended PCB Layout for 80QFP Pierce Oscillator Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 72 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.1 Introduction The Port Integration Module establishes the interface between the peripheral modules and the I/O pins for all ports.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.1.2 Block Diagram Figure 2-1 is a block diagram of the PIM.
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Chapter 2 Port Integration Module (PIM9C32) Block Description when mapping PWM channels to Port T in an 80QFP option, the associated PWM channels are then mapped to both Port P and Port T. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.2 Signal Description This section lists and describes the signals that do connect off-chip. Table 2-1 shows all pins and their functions that are controlled by the PIM module. If there is more than one function associated to a pin, the priority is indicated by the position in the table from top (highest priority) to down (lowest priority). Table 2-1.
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Chapter 2 Port Integration Module (PIM9C32) Block Description Table 2-1. Pin Functions and Priorities (continued) Port Pin Name Pin Function PE7 NOACC/ XCLKS/ GPIO PE6 IPIPE1/ MODB/ GPIO PE5 IPIPE0/ MODA/ GPIO PE4 ECLK/GPIO PE3 LSTRB/ TAGLO/ GPIO PE2 R/W/ GPIO PE1 IRQ/GPI PE0 XIRQ/GPI Port E 2.3 Pin Function after Reset Description Refer to MEBI Block Guide. Memory Map and Registers This section provides a detailed description of all registers. 2.3.
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Chapter 2 Port Integration Module (PIM9C32) Block Description Address Name R 0x0006 Reserved W R 0x0007 MODRR W R 0x0008 PTS W SCI R 0x0009 PTIS W R 0x000A DDRS W R 0x000B RDRS W R 0x000C PERS W R 0x000D PPSS W R 0x000E WOMS W R 0x000F Reserved W R W 0x0010 PTM MSCAN / SPI R 0x0011 PTIM W R 0x0012 DDRM W R 0x0013 RDRM W R 0x0014 PERM W R 0x0015 PPSM W R 0x0016 WOMM W R 0x0017 Reserved W R 0x0018 PTP W PWM R 0x0019 PTIP W Bit 7 0 6 0 5 0 4 0 0 0 0 0 0 0 0 — 0 — 0 — 0 — 0 0 0 0 0 0 0
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Chapter 2 Port Integration Module (PIM9C32) Block Description Address Name 0x001A DDRP 0x001B RDRP 0x001C PERP 0x001D PPSP 0x001E PIEP 0x001F PIFP 0x0020– Reserved 0x0027 0x0028 PTJ 0x0029 PTIJ 0x002A DDRJ 0x002B RDRJ 0x002C PERJ 0x002D PPSJ 0x002E PIEJ 0x002F PIFJ 0x0030 PTAD 0x0031 PTIAD 0x0032 DDRAD 0x0033 RDRAD 0x0034 PERAD 0x0035 PPSAD 0x0036– Reserved 0x003F R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 6 5
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2 Register Descriptions Table 2-2 summarizes the effect on the various configuration bits — data direction (DDR), input/output level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports. The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1 Port T Registers 2.3.2.1.1 Port T I/O Register (PTT) Module Base + 0x0000 7 6 5 4 3 2 1 0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 PWM4 PWM3 PWM2 PWM1 PWM0 0 0 0 0 0 R W TIM PWM Reset 0 0 0 = Unimplemented or Reserved Figure 2-3. Port T I/O Register (PTT) Read: Anytime. Write: Anytime.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1.2 Port T Input Register (PTIT) Module Base + 0x0001 R 7 6 5 4 3 2 1 0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 — — — — — — — — W Reset = Unimplemented or Reserved Figure 2-4. Port T Input Register (PTIT) Read: Anytime. Write: Never, writes to this register have no effect. Table 2-4.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1.4 Port T Reduced Drive Register (RDRT) Module Base + 0x0003 7 6 5 4 3 2 1 0 RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 2-6. Port T Reduced Drive Register (RDRT) Read: Anytime. Write: Anytime. Table 2-6.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1.6 Port T Polarity Select Register (PTTST) Module Base + 0x0005 7 6 5 4 3 2 1 0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 R W Reset Figure 2-8. Port T Polarity Select Register (PPST) Read: Anytime. Write: Anytime. Table 2-8. PPST Field Descriptions Field Description 7–0 PPST[7:0] Pull Select Port T — This register selects whether a pull-down or a pull-up device is connected to the pin.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2 Port S Registers 2.3.2.2.1 Port S I/O Register (PTS) Module Base + 0x0008 R 7 6 5 4 0 0 0 0 3 2 1 0 PTS3 PTS2 PTS1 PTS0 W SCI — — — — — — TXD RXD Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-10. Port S I/O Register (PTS) Read: Anytime. Write: Anytime.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2.3 Port S Data Direction Register (DDRS) Module Base + 0x000A R 7 6 5 4 0 0 0 0 3 2 1 0 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 2-12. Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. Table 2-11. DDRS Field Descriptions Field 3–0 DDRS[3:0] Description Direction Register Port S — This register configures each port S pin as either input or output.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2.4 Port S Reduced Drive Register (RDRS) Module Base + 0x000B R 7 6 5 4 0 0 0 0 3 2 1 0 RDRS3 RDRS2 RDRS1 RDRS0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 2-13. Port S Reduced Drive Register (RDRS) Read: Anytime. Write: Anytime. Table 2-12.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2.6 Port S Polarity Select Register (PPSS) Module Base + 0x000D R 7 6 5 4 0 0 0 0 3 2 1 0 PPSS3 PPSS2 PPSS1 PPSS0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 2-15. Port S Polarity Select Register (PPSS) Read: Anytime. Write: Anytime. Table 2-14.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3 Port M Registers 2.3.2.3.1 Port M I/O Register (PTM) Module Base + 0x0010 R 7 6 0 0 5 4 3 2 1 0 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 W MSCAN/ SPI — — SCK MOSI SS MISO TXCAN RXCAN Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-17. Port M I/O Register (PTM) Read: Anytime. Write: Anytime.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3.3 Port M Data Direction Register (DDRM) Module Base + 0x0012 R 7 6 0 0 5 4 3 2 1 0 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 0 0 0 0 0 0 W Reset — — = Unimplemented or Reserved Figure 2-19. Port M Data Direction Register (DDRM) Read: Anytime. Write: Anytime. Table 2-17.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3.4 Port M Reduced Drive Register (RDRM) Module Base + 0x0013 R 7 6 0 0 5 4 3 2 1 0 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 0 0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 2-20. Port M Reduced Drive Register (RDRM) Read: Anytime. Write: Anytime. Table 2-18.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3.6 Port M Polarity Select Register (PPSM) Module Base + 0x0015 R 7 6 0 0 5 4 3 2 1 0 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 2-22. Port M Polarity Select Register (PPSM) Read: Anytime. Write: Anytime. Table 2-20.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4 Port P Registers 2.3.2.4.1 Port P I/O Register (PTP) Module Base + 0x0018 7 6 5 4 3 2 1 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PWM — — PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Reset 0 0 0 0 0 0 0 0 R W Figure 2-24. Port P I/O Register (PTP) Read: Anytime. Write: Anytime.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4.3 Port P Data Direction Register (DDRP) Module Base + 0x001A 7 6 5 4 3 2 1 0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-26. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. Table 2-22. DDRP Field Descriptions Field Description 7–0 DDRP[7:0] Data Direction Port P — This register configures each port P pin as either input or output.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4.5 Port P Pull Device Enable Register (PERP) Module Base + 0x001C 7 6 5 4 3 2 1 0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-28. Port P Pull Device Enable Register (PERP) Read: Anytime. Write: Anytime. Table 2-24.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4.7 Port P Interrupt Enable Register (PIEP) Module Base + 0x001E 7 6 5 4 3 2 1 0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-30. Port P Interrupt Enable Register (PIEP) Read: Anytime. Write: Anytime. Table 2-26.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5 Port J Registers 2.3.2.5.1 Port J I/O Register (PTJ) Module Base + 0x0028 7 6 PTJ7 PTJ6 0 0 R 5 4 3 2 1 0 0 0 0 0 0 0 — — — — — — W Reset = Unimplemented or Reserved Figure 2-32. Port J I/O Register (PTJ) Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. 2.3.2.5.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5.3 Port J Data Direction Register (DDRJ) Module Base + 0x002A 7 6 DDRJ7 DDRJ6 0 0 R 5 4 3 2 1 0 0 0 0 0 0 0 — — — — — — W Reset = Unimplemented or Reserved Figure 2-34. Port J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. Table 2-28. DDRJ Field Descriptions Field Description 7–6 DDRJ[7:6] Data Direction Port J — This register configures port pins J[7:6] as either input or output.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5.5 Port J Pull Device Enable Register (PERJ) Module Base + 0x002C 7 6 PERJ7 PERJ6 0 0 R 5 4 3 2 1 0 0 0 0 0 0 0 — — — — — — W Reset = Unimplemented or Reserved Figure 2-36. Port J Pull Device Enable Register (PERJ) Read: Anytime. Write: Anytime. Table 2-30.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5.7 Port J Interrupt Enable Register (PIEJ) Module Base + 0x002E 7 6 PIEJ7 PIEJ6 0 0 R 5 4 3 2 1 0 0 0 0 0 0 0 — — — — — — W Reset = Unimplemented or Reserved Figure 2-38. Port J Interrupt Enable Register (PIEJ) Read: Anytime. Write: Anytime. Table 2-32.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.6 Port AD Registers 2.3.2.6.1 Port AD I/O Register (PTAD) Module Base + 0x0030 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0 0 0 0 0 0 0 0 R W Reset Figure 2-40. Port AD I/O Register (PTAD) Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. 2.3.2.6.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.6.3 Port AD Data Direction Register (DDRAD) Module Base + 0x0032 7 6 5 4 3 2 1 0 DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 0 0 0 0 0 0 0 0 R W Reset Figure 2-42. Port AD Data Direction Register (DDRAD) Read: Anytime. Write: Anytime. Table 2-34. DDRAD Field Descriptions Field Description 7–0 Data Direction Port AD — This register configures port pins AD[7:0] as either input or output.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.6.5 Port AD Pull Device Enable Register (PERAD) Module Base + 0x0034 7 6 5 4 3 2 1 0 PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 0 0 0 0 0 0 0 0 R W Reset Figure 2-44. Port AD Pull Device Enable Register (PERAD) Read: Anytime. Write: Anytime. Table 2-36.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.4 Functional Description Each pin can act as general purpose I/O. In addition the pin can act as an output from a peripheral module or an input to a peripheral module. A set of configuration registers is common to all ports. All registers can be written at any time, however a specific configuration might not become active. Example: Selecting a pull-up resistor. This resistor does not become active while the port is used as a pushpull output.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.4.1.4 Reduced Drive Register If the port is used as an output the register allows the configuration of the drive strength. 2.4.1.5 Pull Device Enable Register This register turns on a pull-up or pull-down device. It becomes only active if the pin is used as an input or as a wired-or output. 2.4.1.6 Polarity Select Register This register selects either a pull-up or pull-down device if enabled.
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.4.2.5 Port P The PWM module is connected to port P. Port P pins can be used as PWM outputs. Further the Keypad Wake-Up function is implemented on pins PP[7:0]. During reset, port P pins are configured as highimpedance inputs. Port P offers 8 general purpose I/O pins with edge triggered interrupt capability in wired-or fashion.
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Chapter 2 Port Integration Module (PIM9C32) Block Description A valid edge on input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock is generated by a single RC oscillator in the Port Integration Module.
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Chapter 2 Port Integration Module (PIM9C32) Block Description Table 2-39. Port Reset State Summary Reset States Port Data Direction Pull Mode Reduced Drive Wired-OR Mode Interrupt T Input Hi-z Disabled n/a n/a S Input Pull up Disabled Disabled n/a M Input Pull up Disabled Disabled n/a P Input Hi-z Disabled n/a Disabled J Input Hi-z Disabled n/a Disabled A B Refer to MEBI Block Guide for details. E BKGD pin 2.6 Refer to BDM Block Guide for details.
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.1 Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core platform. The block diagram of the MMC is shown in Figure 3-1.
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.1.1 • • • • • • • • • • • 3.1.
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Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-1. MMC Memory Map (continued) Address Offset 0x0017 Register Reserved Access — . . . . — 0x001C Memory Size Register 0 (MEMSIZ0) R 0x001D Memory Size Register 1 (MEMSIZ1) R . . . . 0x0030 Program Page Index Register (PPAGE) 0x0031 Reserved Freescale Semiconductor R/W — MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2.1 Initialization of Internal RAM Position Register (INITRM) Module Base + 0x0010 Starting address location affected by INITRG register setting. 7 6 5 4 3 RAM15 RAM14 RAM13 RAM12 RAM11 0 0 0 0 1 R 2 1 0 0 0 RAMHAL W Reset 0 0 1 = Unimplemented or Reserved Figure 3-3.
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2.2 Initialization of Internal Registers Position Register (INITRG) Module Base + 0x0011 Starting address location affected by INITRG register setting. 7 R 6 5 4 3 REG14 REG13 REG12 REG11 0 0 0 0 0 2 1 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 3-4.
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2.3 Initialization of Internal EEPROM Position Register (INITEE) Module Base + 0x0012 Starting address location affected by INITRG register setting. 7 6 5 4 3 EE15 EE14 EE13 EE12 EE11 — — — — — R 2 1 0 0 0 EEON W Reset1 — — — 1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register.
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2.4 Miscellaneous System Control Register (MISC) Module Base + 0x0013 Starting address location affected by INITRG register setting. R 7 6 5 4 0 0 0 0 3 2 1 0 EXSTR1 EXSTR0 ROMHM ROMON W Reset: Expanded or Emulation 0 0 0 0 1 1 0 —1 Reset: Peripheral or Single Chip 0 0 0 0 1 1 0 1 Reset: Special Test 0 0 0 0 1 1 0 0 1. The reset state of this bit is determined at the chip integration level.
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Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-6. External Stretch Bit Definition 3.3.2.5 Stretch Bit EXSTR1 Stretch Bit EXSTR0 Number of E Clocks Stretched 0 0 0 0 1 1 1 0 2 1 1 3 Reserved Test Register 0 (MTST0) Module Base + 0x0014 Starting address location affected by INITRG register setting. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 3-7.
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2.7 Memory Size Register 0 (MEMSIZ0) Module Base + 0x001C Starting address location affected by INITRG register setting. 7 R REG_SW0 6 5 4 3 2 1 0 0 EEP_SW1 EEP_SW0 0 RAM_SW2 RAM_SW1 RAM_SW0 — — — — — — — W Reset — = Unimplemented or Reserved Figure 3-9. Memory Size Register 0 (MEMSIZ0) Read: Anytime Write: Writes have no effect Reset: Defined at chip integration, see device overview section.
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Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-9. Allocated RAM Memory Space (continued) ram_sw2:ram_sw0 Allocated RAM Space RAM Mappable Region INITRM Bits Used RAM Reset Base Address(1) 011 8K bytes 8K bytes 100 10K bytes RAM[15:13] 0x0000 16K bytes 2 RAM[15:14] 0x1800 2 RAM[15:14] 0x1000 RAM[15:14] 0x0800 101 12K bytes 16K bytes 110 14K bytes 16K bytes 2 111 16K bytes 16K bytes RAM[15:14] 0x0000 1.
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Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-10. MEMSIZ0 Field Descriptions Field Description 7:6 Allocated System FLASH or ROM Physical Memory Space — The allocated system FLASH or ROM ROM_SW[1:0] physical memory space is as given in Table 3-11. 1:0 Allocated Off-Chip FLASH or ROM Memory Space — The allocated off-chip FLASH or ROM memory space PAG_SW[1:0] size is as given in Table 3-12. Table 3-11.
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2.9 Program Page Index Register (PPAGE) Module Base + 0x0030 Starting address location affected by INITRG register setting. R 7 6 0 0 5 4 3 2 1 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 — — — — — — W Reset1 — — 1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register. = Unimplemented or Reserved Figure 3-11.
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Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-14. Program Page Index Register Bits 3.4 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 Program Space Selected 0 0 0 0 0 0 16K page 0 0 0 0 0 0 1 16K page 1 0 0 0 0 1 0 16K page 2 0 0 0 0 1 1 16K page 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 3 Module Mapping Control (MMCV4) Block Description vector spaces, expansion windows, and on-chip memory are mapped so that their address ranges do not overlap. The MMC will make only one select signal active at any given time. This activation is based upon the priority outlined in Table 3-15. If two or more blocks share the same address space, only the select signal for the block with the highest priority will become active.
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Chapter 3 Module Mapping Control (MMCV4) Block Description unimplemented locations within the register space or to locations that are removed from the map (i.e., ports A and B in expanded modes) will not cause this signal to become active. When the EMK bit is clear, this pin is used for general purpose I/O. 3.4.3 Memory Expansion The HCS12 core architecture limits the physical address space available to 64K bytes.
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Chapter 3 Module Mapping Control (MMCV4) Block Description The PPAGE register holds the page select value for the program page window. The value of the PPAGE register can be manipulated by normal read and write (some devices don’t allow writes in some modes) instructions as well as the CALL and RTC instructions. Control registers, vector spaces, and a portion of on-chip memory are located in unpaged portions of the 64K byte physical address space.
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Chapter 3 Module Mapping Control (MMCV4) Block Description During the execution of an RTC instruction, the CPU: • Pulls the old PPAGE value from the stack • Pulls the 16-bit return address from the stack and loads it into the PC • Writes the old PPAGE value into the PPAGE register • Refills the queue and resumes execution at the return address This sequence is uninterruptable; an RTC can be executed from anywhere in memory, even from a different page of extended memory in the expansion window.
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Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-20. 48K Byte Physical FLASH/ROM Allocated Address Space Page Window Access ROMHM ECS XAB19:14 0x0000–0x3FFF N/A N/A 1 0x3D 0x4000–0x7FFF N/A 0 0 0x3E N/A 1 1 0x8000–0xBFFF 0xC000–0xFFFF External N/A 1 Internal N/A 0 N/A N/A 0 PIX[5:0] 0x3F Table 3-21.
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Chapter 3 Module Mapping Control (MMCV4) Block Description A graphical example of a memory paging for a system configured as 1M byte on-chip FLASH/ROM with 64K allocated physical space is given in Figure 3-12.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.1 Introduction This section describes the functionality of the multiplexed external bus interface (MEBI) sub-block of the S12 core platform. The functionality of the module is closely coupled with the S12 CPU and the memory map controller (MMC) sub-blocks. Figure 4-1 is a block diagram of the MEBI. In Figure 4-1, the signals on the right hand side represent pins that are accessible externally. On some chips, these may not all be bonded out.
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Internal Bus Addr[19:0] EXT BUS I/F CTL Data[15:0] ADDR DATA Port K ADDR PK[7:0]/ECS/XCS/X[19:14] Port A REGS PA[7:0]/A[15:8]/ D[15:8]/D[7:0] Port B Chapter 4 Multiplexed External Bus Interface (MEBIV3) PB[7:0]/A[7:0]/ D[7:0] (Control) ADDR DATA CPU pipe info PIPE CTL IRQ interrupt XIRQ interrupt IRQ CTL TAG CTL BDM tag info mode Port E ECLK CTL PE[7:2]/NOACC/ IPIPE1/MODB/CLKTO IPIPE0/MODA/ ECLK/ LSTRB/TAGLO R/W PE1/IRQ PE0/XIRQ BKGD BKGD/MODC/TAGHI Control signal(s) Data signal (u
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.1.2 • • • • • • • • 4.2 Modes of Operation Normal expanded wide mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. Normal expanded narrow mode Ports A and B are configured as a 16-bit address bus and port A is multiplexed with 8-bit data.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) . Table 4-1. External System Pins Associated With MEBI Pin Name BKGD/MODC/ TAGHI PA7/A15/D15/D7 thru PA0/A8/D8/D0 PB7/A7/D7 thru PB0/A0/D0 PE7/NOACC PE6/IPIPE1/ MODB/CLKTO PE5/IPIPE0/MODA 132 Pin Functions Description MODC At the rising edge on RESET, the state of this pin is registered into the MODC bit to set the mode. (This pin always has an internal pullup.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Table 4-1. External System Pins Associated With MEBI (continued) Pin Name PE4/ECLK PE3/LSTRB/ TAGLO PE2/R/W PE1/IRQ PE0/XIRQ PK7/ECS PK6/XCS PK5/X19 thru PK0/X14 Pin Functions Description PE4 General-purpose I/O pin, see PORTE and DDRE registers. ECLK Bus timing reference clock, can operate as a free-running clock at the system clock rate or to produce one low-high clock per visible access, with the high period stretched for slow accesses.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.1 Module Memory Map Table 4-2. MEBI Memory Map Address Offset 4.3.2 4.3.2.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Read: Anytime when register is in the map Write: Anytime when register is in the map Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in singlechip mode, these pins can be used as general-purpose I/O. Data direction register A (DDRA) determines the primary direction of each pin.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.3 Data Direction Register A (DDRA) Module Base + 0x0002 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 4-4. Data Direction Register A (DDRA) Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port A.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.4 Data Direction Register B (DDRB) Module Base + 0x0003 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 4-5. Data Direction Register B (DDRB) Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port B.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.5 Reserved Registers Module Base + 0x0004 Starting address location affected by INITRG register setting. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 4-6. Reserved Register Module Base + 0x0005 Starting address location affected by INITRG register setting.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) These register locations are not used (reserved). All unused registers and bits in this block return logic 0s when read. Writes to these registers have no effect. These registers are not in the on-chip map in special peripheral mode. 4.3.2.6 Port E Data Register (PORTE) Module Base + 0x0008 Starting address location affected by INITRG register setting.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) NOTE To ensure that you read the value present on the PORTE pins, always wait at least one cycle after writing to the DDRE register before reading from the PORTE register. 4.3.2.7 Data Direction Register E (DDRE) Module Base + 0x0009 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 Bit 7 6 5 4 3 Bit 2 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 4-11.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.8 Port E Assignment Register (PEAR) Module Base + 0x000A Starting address location affected by INITRG register setting.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Table 4-6. PEAR Field Descriptions Field Description 7 NOACCE CPU No Access Output Enable Normal: write once Emulation: write never Special: write anytime 1 The associated pin (port E, bit 7) is general-purpose I/O. 0 The associated pin (port E, bit 7) is output and indicates whether the cycle is a CPU free cycle. This bit has no effect in single-chip or special peripheral modes.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.9 Mode Register (MODE) Module Base + 0x000B Starting address location affected by INITRG register setting.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Table 4-7. MODE Field Descriptions Field Description 7:5 MOD[C:A] Mode Select Bits — These bits indicate the current operating mode. If MODA = 1, then MODC, MODB, and MODA are write never. If MODC = MODA = 0, then MODC, MODB, and MODA are writable with the exception that you cannot change to or from special peripheral mode If MODC = 1, MODB = 0, and MODA = 0, then MODC is write never.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Table 4-8.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE These bits have no effect when the associated pin(s) are outputs. (The pull resistors are inactive.) Table 4-9. PUCR Field Descriptions Field Description 7 PUPKE Pull resistors Port K Enable 0 Port K pull resistors are disabled. 1 Enable pull resistors for port K input pins.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Table 4-10. RDRIV Field Descriptions Field Description 7 RDRK Reduced Drive of Port K 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. 4 RDPE Reduced Drive of Port E 0 All port E output pins have full drive enabled. 1 All port E output pins have reduced drive enabled. 1 RDPB Reduced Drive of Port B 0 All port B output pins have full drive enabled.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.13 Reserved Register Module Base + 0x000F Starting address location affected by INITRG register setting. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 4-17. Reserved Register This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to this register have no effect.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.15 Port K Data Register (PORTK) Module Base + 0x0032 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 ECS XCS XAB19 XAB18 XAB17 XAB16 XAB15 XAB14 R W Reset Alternate Pin Function Figure 4-19. Port K Data Register (PORTK) Read: Anytime Write: Anytime This port is associated with the internal memory expansion emulation pins.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.16 Port K Data Direction Register (DDRK) Module Base + 0x0033 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 4-20. Port K Data Direction Register (DDRK) Read: Anytime Write: Anytime This register determines the primary direction for each port K pin configured as general-purpose I/O.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Table 4-15. Access Type vs. Bus Control Pins 4.4.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) There are two basic types of operating modes: 1. Normal modes: Some registers and bits are protected against accidental changes. 2. Special modes: Allow greater access to protected control registers and bits for special purposes such as testing. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. Some aspects of Port E are not mode dependent.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.4.3.1.2 Normal Expanded Wide Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pull resistors enabled).
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.4.3.2 Special Operating Modes There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. 4.4.3.2.1 Special Single-Chip Mode When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does not fetch the reset vector and execute application code as it would in other modes.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) mode. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both functions. 4.4.4 Internal Visibility Internal visibility is available when the MCU is operating in expanded wide modes or emulation narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes.
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Chapter 5 Interrupt (INTV1) Block Description 5.1 Introduction This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform. A block diagram of the interrupt sub-block is shown in Figure 5-1.
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Chapter 5 Interrupt (INTV1) Block Description The interrupt sub-block decodes the priority of all system exception requests and provides the applicable vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a nonmaskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug mode request, and three system reset vector requests. All interrupt related exception requests are managed by the interrupt sub-block (INT). 5.1.
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Chapter 5 Interrupt (INTV1) Block Description 5.2 External Signal Description Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and XIRQ pin data. 5.3 Memory Map and Register Definition Detailed descriptions of the registers and associated bits are given in the subsections that follow. 5.3.1 Module Memory Map Table 5-1.
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Chapter 5 Interrupt (INTV1) Block Description Table 5-2. ITCR Field Descriptions Field Description 4 WRTINT Write to the Interrupt Test Registers Read: anytime Write: only in special modes and with I-bit mask and X-bit mask set. 0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs. 1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers instead.
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Chapter 5 Interrupt (INTV1) Block Description Table 5-3. ITEST Field Descriptions Field Description 7:0 INT[E:0] Interrupt TEST Bits — These registers are used in special modes for testing the interrupt logic and priority independent of the system configuration. Each bit is used to force a specific interrupt vector by writing it to a logic 1 state. Bits are named INTE through INT0 to indicate vectors 0xFFxE through 0xFFx0.
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Chapter 5 Interrupt (INTV1) Block Description 5.4.1 Low-Power Modes The INT does not contain any user-controlled options for reducing power consumption. The operation of the INT in low-power modes is discussed in the following subsections. 5.4.1.1 Operation in Run Mode The INT does not contain any options for reducing power in run mode. 5.4.1.
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Chapter 5 Interrupt (INTV1) Block Description 5.6.3 Interrupt Priority Decoder The priority decoder evaluates all interrupts pending and determines their validity and priority. When the CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt request. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt request could override the original exception that caused the CPU to request the vector.
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Chapter 5 Interrupt (INTV1) Block Description 164 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.1 Introduction This section describes the functionality of the background debug module (BDM) sub-block of the HCS12 core platform. A block diagram of the BDM is shown in Figure 6-1. HOST SYSTEM BKGD 16-BIT SHIFT REGISTER ADDRESS ENTAG BDMACT INSTRUCTION DECODE AND EXECUTION TRACE SDV ENBDM BUS INTERFACE AND CONTROL LOGIC DATA CLOCKS STANDARD BDM FIRMWARE LOOKUP TABLE CLKSW Figure 6-1.
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Chapter 6 Background Debug Module (BDMV4) Block Description • • • • • • • Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 15 firmware commands execute from the standard BDM firmware lookup table Instruction tagging capability Software control of BDM operation during wait mode Software selectable clocks When secured, hardware commands are allowed to access the register space in special single-chip mode, if the FLASH and EEPROM
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.2 External Signal Description A single-wire interface pin is used to communicate with the BDM system. Two additional pins are used for instruction tagging. These pins are part of the multiplexed external bus interface (MEBI) sub-block and all interfacing between the MEBI and BDM is done within the core interface boundary. Functional descriptions of the pins are provided below for completeness.
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.3 Memory Map and Register Definition A summary of the registers associated with the BDM is shown in Figure 6-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Detailed descriptions of the registers and associated bits are given in the subsections that follow. 6.3.1 Module Memory Map Table 6-1.
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.3.
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.3.2.1 BDM Status Register (BDMSTS) 0xFF01 7 R 6 5 BDMACT ENBDM 4 3 SDV TRACE ENTAG 2 1 0 UNSEC 0 0(2) 0 0 0 0 0 0 0 CLKSW W Reset: Special single-chip mode: Special peripheral mode: All other modes: 1(1) 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 0 0 0 0 = Implemented (do not alter) Figure 6-3. BDM Status Register (BDMSTS) Note: 1.
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Chapter 6 Background Debug Module (BDMV4) Block Description Table 6-2. BDMSTS Field Descriptions Field Description 7 ENBDM Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are allowed. 0 BDM disabled 1 BDM enabled Note: ENBDM is set by the firmware immediately out of reset in special single-chip mode.
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Chapter 6 Background Debug Module (BDMV4) Block Description Table 6-2. BDMSTS Field Descriptions (continued) Field Description 2 CLKSW Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A 150 cycle delay at the clock speed that is active during the data portion of the command will occur before the new clock source is guaranteed to be active.
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.3.2.2 BDM CCR Holding Register (BDMCCR) 0xFF06 7 6 5 4 3 2 1 0 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 0 0 0 0 0 0 0 0 R W Reset Figure 6-4. BDM CCR Holding Register (BDMCCR) Read: All modes Write: All modes NOTE When BDM is made active, the CPU stores the value of the CCR register in the BDMCCR register.
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.4 Functional Description The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands, namely, hardware commands and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 6.4.3, “BDM Hardware Commands.” Target system memory includes all memory that is accessible by the CPU.
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Chapter 6 Background Debug Module (BDMV4) Block Description block, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed.
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Chapter 6 Background Debug Module (BDMV4) Block Description The BDM hardware commands are listed in Table 6-5. Table 6-5. Hardware Commands Opcode (hex) Data Description BACKGROUND 90 None Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. ACK_ENABLE D5 None Enable handshake. Issues an ACK pulse after the command is executed. ACK_DISABLE D6 None Disable handshake. This command does not issue an ACK pulse.
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Chapter 6 Background Debug Module (BDMV4) Block Description firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 6-6. Table 6-6. Firmware Commands Command(1) Opcode (hex) Data Description READ_NEXT 62 16-bit data out Increment X by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator.
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Chapter 6 Background Debug Module (BDMV4) Block Description NOTE 16-bit misaligned reads and writes are not allowed. If attempted, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For hardware data read commands, the external host must wait 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out.
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Chapter 6 Background Debug Module (BDMV4) Block Description HARDWARE READ 8 BITS AT ∼16 TC/BIT 16 BITS AT ∼16 TC/BIT COMMAND ADDRESS 150-BC DELAY 16 BITS AT ∼16 TC/BIT DATA NEXT COMMAND 150-BC DELAY HARDWARE WRITE COMMAND ADDRESS DATA NEXT COMMAND 44-BC DELAY FIRMWARE READ COMMAND NEXT COMMAND DATA 32-BC DELAY FIRMWARE WRITE COMMAND DATA NEXT COMMAND 64-BC DELAY GO, TRACE COMMAND NEXT COMMAND BC = BUS CLOCK CYCLES TC = TARGET CLOCK CYCLES Figure 6-6. BDM Command Structure 6.4.
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Chapter 6 Background Debug Module (BDMV4) Block Description earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 6-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time.
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Chapter 6 Background Debug Module (BDMV4) Block Description CLOCK TARGET SYSTEM HOST DRIVE TO BKGD PIN TARGET SYSTEM SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN EARLIEST START OF NEXT BIT Figure 6-8. BDM Target-to-Host Serial Bit Timing (Logic 1) Figure 6-9 shows the host receiving a logic 0 from the target.
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.4.7 Serial Interface Hardware Handshake Protocol BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Because the BDM clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU.
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Chapter 6 Background Debug Module (BDMV4) Block Description Figure 6-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation.
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.4.8 Hardware Handshake Abort Procedure The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse.
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Chapter 6 Background Debug Module (BDMV4) Block Description READ_BYTE CMD IS ABORTED BY THE SYNC REQUEST (OUT OF SCALE) BKGD PIN READ_BYTE SYNC RESPONSE FROM THE TARGET (OUT OF SCALE) MEMORY ADDRESS HOST READ_STATUS TARGET HOST BDM DECODE AND STARTS TO EXECUTES THE READ_BYTE CMD TARGET NEW BDM COMMAND HOST TARGET NEW BDM COMMAND Figure 6-12. ACK Abort Procedure at the Command Level Figure 6-13 shows a conflict between the ACK pulse and the SYNC request pulse.
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Chapter 6 Background Debug Module (BDMV4) Block Description The commands are described as follows: • ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. • ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol.
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.4.9 SYNC — Request Timed Reference Pulse The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1.
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Chapter 6 Background Debug Module (BDMV4) Block Description If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Upon return to standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. 6.4.11 Instruction Tagging The instruction queue and cycle-by-cycle CPU activity are reconstructible in real time or from trace history that is captured by a logic analyzer.
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Chapter 6 Background Debug Module (BDMV4) Block Description If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the behavior where the BDC is running in a frequency much greater than the CPU frequency.
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Chapter 6 Background Debug Module (BDMV4) Block Description 190 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 7 Debug Module (DBGV1) Block Description 7.1 Introduction This section describes the functionality of the debug (DBG) sub-block of the HCS12 core platform. The DBG module is designed to be fully compatible with the existing BKP_HCS12_A module (BKP mode) and furthermore provides an on-chip trace buffer with flexible triggering capability (DBG mode). The DBG module provides for non-intrusive debug of application software. The DBG module is optimized for the HCS12 16-bit architecture. 7.1.
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Chapter 7 Debug Module (DBGV1) Block Description The DBG in DBG mode includes these distinctive features: • Three comparators (A, B, and C) — Dual mode, comparators A and B used to compare addresses — Full mode, comparator A compares address and comparator B compares data — Can be used as trigger and/or breakpoint — Comparator C used in LOOP1 capture mode or as additional breakpoint • Four capture modes — Normal mode, change-of-flow information is captured based on trigger specification — Loop1 mode, compa
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Chapter 7 Debug Module (DBGV1) Block Description — — — — 7.1.2 Data associated with event B trigger modes Detail report mode stores address and data for all cycles except program (P) and free (f) cycles Current instruction address when in profiling mode BGND is not considered a change-of-flow (cof) by the debugger Modes of Operation There are two main modes of operation: breakpoint mode and debug mode. Each one is mutually exclusive of the other and selected via a software programmable control bit.
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Chapter 7 Debug Module (DBGV1) Block Description CLOCKS AND CONTROL SIGNALS BKP CONTROL SIGNALS CONTROL BLOCK BREAKPOINT MODES AND GENERATION OF SWI, FORCE BDM, AND TAGS ...... RESULTS SIGNALS CONTROL SIGNALS READ/WRITE CONTROL CONTROL BITS ......
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Chapter 7 Debug Module (DBGV1) Block Description DBG READ DATA BUS ADDRESS BUS ADDRESS/DATA/CONTROL REGISTERS CONTROL WRITE DATA BUS READ DATA BUS READ/WRITE TRACER BUFFER CONTROL LOGIC MATCH_A COMPARATOR A MATCH_B COMPARATOR B DBG MODE ENABLE CONTROL MATCH_C LOOP1 COMPARATOR C TAG FORCE CHANGE-OF-FLOW INDICATORS MCU IN BDM DETAIL EVENT ONLY STORE CPU PROGRAM COUNTER POINTER INSTRUCTION LAST CYCLE M U X REGISTER BUS CLOCK WRITE DATA BUS M U X READ DATA BUS M U X LAST INSTRUCTION ADDRES
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Chapter 7 Debug Module (DBGV1) Block Description 7.3 Memory Map and Register Definition A summary of the registers associated with the DBG sub-block is shown in Figure 7-3. Detailed descriptions of the registers and bits are given in the subsections that follow. 7.3.1 Module Memory Map Table 7-2.
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Chapter 7 Debug Module (DBGV1) Block Description Name(1) R 0x0022 DBGTBH W 0x0023 DBGTBL W 0x0024 DBGCNT R R R W 0x0026 DBGCCH(2) W 0x0028 DBGC2 BKPCT0 0x0029 DBGC3 BKPCT1 0x002A DBGCAX BKP0X 0x002B DBGCAH BKP0H 0x002C DBGCAL BKP0L 0x002D DBGCBX BKP1X 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBF 0 CNT W 0x0025 DBGCCX((2)) 0x0027 DBGCCL(2) Bit 7 R R W PAGSEL EXTCMP Bit 15 14 13 12
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Chapter 7 Debug Module (DBGV1) Block Description 1. The DBG module is designed for backwards compatibility to existing BKP modules. Register and bit names have changed from the BKP module. This column shows the DBG register name, as well as the BKP register name for reference. 2. Comparator C can be used to enhance the BKP mode by providing a third breakpoint. 7.3.2.1 Debug Control Register 1 (DBGC1) NOTE All bits are used in DBG mode only.
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Chapter 7 Debug Module (DBGV1) Block Description Table 7-3. DBGC1 Field Descriptions (continued) Field Description 3 DBGBRK DBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint based on comparator A and B to the CPU upon completion of a tracing session. Please refer to Section 7.4.3, “Breakpoints,” for further details.
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Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.2 Debug Status and Control Register (DBGSC) Module Base + 0x0021 Starting address location affected by INITRG register setting. R 7 6 5 4 AF BF CF 0 3 2 1 0 0 0 TRG W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-5. Debug Status and Control Register (DBGSC) Table 7-5. DBGSC Field Descriptions Field Description 7 AF Trigger A Match Flag — The AF bit indicates if trigger A match condition was met since arming.
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Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.3 Debug Trace Buffer Register (DBGTB) Module Base + 0x0022 Starting address location affected by INITRG register setting. R 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 u u u u u u u u W Reset = Unimplemented or Reserved Figure 7-6. Debug Trace Buffer Register High (DBGTBH) Module Base + 0x0023 Starting address location affected by INITRG register setting.
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Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.4 Debug Count Register (DBGCNT) Module Base + 0x0024 Starting address location affected by INITRG register setting. R 7 6 TBF 0 0 0 5 4 3 2 1 0 0 0 0 CNT W Reset 0 0 0 = Unimplemented or Reserved Figure 7-8. Debug Count Register (DBGCNT) Table 7-8. DBGCNT Field Descriptions Field Description 7 TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more words of data since it was last armed.
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Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.5 Debug Comparator C Extended Register (DBGCCX) Module Base + 0x0025 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 0 0 0 R PAGSEL EXTCMP W Reset 0 0 0 0 0 Figure 7-9. Debug Comparator C Extended Register (DBGCCX) Table 7-10. DBGCCX Field Descriptions Field Description 7:6 PAGSEL Page Selector Field — In both BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 7-11.
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Chapter 7 Debug Module (DBGV1) Block Description DBGCXX 7 DBGCXH[15:12] EXTCMP 6 BIT 15 BIT 14 XAB16 XAB15 XAB14 PIX2 PIX1 PIX0 0 5 0 4 3 2 1 BIT 0 XAB21 XAB20 XAB19 XAB18 XAB17 PIX7 PIX6 PIX5 PIX4 PIX3 BIT 13 BIT 12 BKP/DBG MODE PAGSEL SEE NOTE 1 PORTK/XAB PPAGE SEE NOTE 2 NOTES: 1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 7-11. 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
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Chapter 7 Debug Module (DBGV1) Block Description Table 7-12. DBGCC Field Descriptions Field Description 15:0 Comparator C Compare Bits — The comparator C compare bits control whether comparator C will compare the address bus bits [15:0] to a logic 1 or logic 0. See Table 7-13. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode. Table 7-13.
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Chapter 7 Debug Module (DBGV1) Block Description Table 7-14. DBGC2 Field Descriptions (continued) Field Description 4 TAGAB Comparator A/B Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint.
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Chapter 7 Debug Module (DBGV1) Block Description Table 7-15. DBGC3 Field Descriptions Field Description 7:6 Breakpoint Mask High Byte for First Address — In dual or full mode, these bits may be used to mask (disable) BKAMB[H:L] the comparison of the high and/or low bytes of the first address breakpoint. The functionality is as given in Table 7-16. The x:0 case is for a full address compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare.
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Chapter 7 Debug Module (DBGV1) Block Description Table 7-15. DBGC3 Field Descriptions (continued) Field Description 1 RWBEN Read/Write Comparator B Enable Bit — The RWBEN bit controls whether read or write comparison is enabled for comparator B. See Section 7.4.2.1.1, “Read or Write Comparison,” for more information. This bit is not useful for tagged operations.
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Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.9 Debug Comparator A Extended Register (DBGCAX) Module Base + 0x002A Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 0 0 0 R PAGSEL EXTCMP W Reset 0 0 0 0 0 Figure 7-15. Debug Comparator A Extended Register (DBGCAX) Table 7-19. DBGCAX Field Descriptions Field Description 7:6 PAGSEL Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 720.
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Chapter 7 Debug Module (DBGV1) Block Description 0 EXTCMP 0 5 4 3 2 1 BIT 0 SEE NOTE 1 PORTK/XAB XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14 PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 PPAGE BKP MODE PAGSEL DBGCXX SEE NOTE 2 NOTES: 1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state). 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Figure 7-16. Comparators A and B Extended Comparison in BKP Mode 7.3.2.
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Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.11 Debug Comparator B Extended Register (DBGCBX) Module Base + 0x002D 7 6 5 4 3 2 1 0 0 0 0 R PAGSEL EXTCMP W Reset 0 0 0 0 0 Figure 7-19. Debug Comparator B Extended Register (DBGCBX) Table 7-22. DBGCBX Field Descriptions Field Description 7:6 PAGSEL Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 711.
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Chapter 7 Debug Module (DBGV1) Block Description Module Base + 0x002F Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 7-21. Debug Comparator B Register Low (DBGCBL) Table 7-23.
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Chapter 7 Debug Module (DBGV1) Block Description DBGC2 being logic 1 or logic 0, respectively. BDM requests have a higher priority than SWI requests. No data breakpoints are allowed in this mode. TAGAB in DBGC2 selects whether the breakpoint mode is forced or tagged. The BKxMBH:L bits in DBGC3 select whether or not the breakpoint is matched exactly or is a range breakpoint. They also select whether the address is matched on the high byte, low byte, both bytes, and/or memory expansion.
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Chapter 7 Debug Module (DBGV1) Block Description NOTE BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. Even if the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled.
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Chapter 7 Debug Module (DBGV1) Block Description control (TBC) block. When PAGSEL = 01, registers DBGCAX, DBGCBX, and DBGCCX are used to match the upper addresses as shown in Table 7-11. NOTE If a tagged-type C breakpoint is set at the same address as an A/B taggedtype trigger (including the initial entry in an inside or outside range trigger), the C breakpoint will have priority and the trigger will not be recognized. 7.4.2.1.
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Chapter 7 Debug Module (DBGV1) Block Description 7.4.2.3 Begin- and End-Trigger The definitions of begin- and end-trigger as used in the DBG module are as follows: • Begin-trigger: Storage in trace buffer occurs after the trigger and continues until 64 locations are filled. • End-trigger: Storage in trace buffer occurs until the trigger, with the least recent data falling out of the trace buffer if more than 64 words are collected. 7.4.2.
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Chapter 7 Debug Module (DBGV1) Block Description least six addresses higher than address A (or B is lower than A) and there are not changes of flow to put these in the queue at the same time, then this operation should trigger properly. 7.4.2.5.4 Event-Only B (Store Data) In the event-only B trigger mode, if the match condition for B is met, the B flag in DBGSC is set and a trigger occurs. The event-only B trigger mode is considered a begin-trigger type and the BEGIN bit in DBGC1 is ignored.
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Chapter 7 Debug Module (DBGV1) Block Description 7.4.2.5.8 Inside Range (A ≤ address ≤ B) In the inside range trigger mode, if the match condition for A and B happen on the same bus cycle, both the A and B flags in DBGSC are set and a trigger occurs. If a match condition on only A or only B occurs no flags are set. If TRGSEL = 1, the inside range is accurate only to word boundaries.
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Chapter 7 Debug Module (DBGV1) Block Description 7.4.2.6 Capture Modes The DBG in DBG mode can operate in four capture modes. These modes are described in the following subsections. 7.4.2.6.1 Normal Mode In normal mode, the DBG module uses comparator A and B as triggering devices. Change-of-flow information or data will be stored depending on TRG in DBGSC. 7.4.2.6.
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Chapter 7 Debug Module (DBGV1) Block Description 7.4.2.6.3 Detail Mode In the detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where his code was in error. 7.4.2.6.
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Chapter 7 Debug Module (DBGV1) Block Description the trigger is at the address of a change-of-flow address the trigger event will not be stored in the trace buffer. 7.4.2.9 Reading Data from Trace Buffer The data stored in the trace buffer can be read using either the background debug module (BDM) module or the CPU provided the DBG module is enabled and not armed. The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid words can be determined.
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Chapter 7 Debug Module (DBGV1) Block Description Table 7-26. Breakpoint Setup 7.4.3.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.1 Introduction The ATD10B8C is an 8-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. The block is designed to be upwards compatible with the 68HC11 standard 8-bit A/D converter. In addition, there are new operating modes that are unique to the HC12 design. 8.1.1 • • • • • • • • • • • • Features 8/10-bit resolution.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.1.2.2 • • • 8.1.3 MCU Operating Modes Stop Mode Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This aborts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time, tSR, before initiating a new ATD conversion sequence.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.2 Signal Description The ATD10B8C has a total of 12 external pins. 8.2.1 AN7 / ETRIG / PAD7 This pin serves as the analog input channel 7. It can be configured to provide an external trigger for the ATD conversion. It can be configured as general-purpose digital I/O. 8.2.2 AN6 / PAD6 This pin serves as the analog input channel 6. It can be configured as general-purpose digital I/O. 8.2.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the ATD10B8C. 8.3.1 Module Memory Map Figure 8-2 gives an overview on all ATD10B8C registers.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Address Name Bit 7 6 5 4 3 2 1 Bit 0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 BIT 8 B
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Address 0x001E Name ATDDR7H Bit 7 6 5 4 3 2 1 Bit 0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 BIT 1 u BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 7 BIT 7 MSB BIT 6 BIT 6 B
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Address Name R 0x001C ATDDR6H Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 W R 0x001D ATDDR6L W R 0x001E ATDDR7H W R 0x001F ATDD
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2 Register Descriptions This section describes in address order all the ATD10B8C registers and their individual bits. 8.3.2.1 Reserved Register (ATDCTL0) Module Base + 0x0000 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 8-3. Reserved Register (ATDCTL0) Read: Always read $00 in normal modes Write: Unimplemented in normal modes 8.3.2.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.3 ATD Control Register 2 (ATDCTL2) This register controls power down, interrupt, and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0002 7 6 5 4 3 2 1 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE 0 0 0 0 0 0 0 R 0 ASCIF W Reset 0 = Unimplemented or Reserved Figure 8-5.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-1. ATDCTL2 Field Descriptions (continued) Field Description 1 ASCIE ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. 0 ASCIF ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 8.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-3. ATDCTL3 Field Descriptions (continued) Field Description 2 FIFO Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-8.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. Module Base + 0x0005 7 6 5 4 DJM DSGN SCAN MULT 0 0 0 0 R 3 2 1 0 CC CB CA 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 8-8.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-10. Available Result Data Formats SRES8 DJM DSGN Result Data Formats Description and Bus Bit Mapping 1 1 1 0 0 0 0 0 1 0 0 1 0 1 X 0 1 X 8-bit / left justified / unsigned — bits 8–15 8-bit / left justified / signed — bits 8–15 8-bit / right justified / unsigned — bits 0–7 10-bit / left justified / unsigned — bits 6–15 10-bit / left justified / signed — bits 6–15 10-bit / right justified / unsigned — bits 0–9 Table 8-11.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the sequence complete flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 R 6 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 0 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 8-9.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-13. ATDSTAT0 Field Descriptions (continued) Field Description 4 FIFOR FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.9 ATD Test Register 1 (ATDTEST1) This register contains the SC bit used to enable special channel conversions. Module Base + 0x0009 R 7 6 5 4 3 2 1 U U U U U U U 0 SC W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-11. ATD Test Register 1 (ATDTEST1) Read: Anytime, returns unpredictable values for Bit 7 and Bit 6 Write: Anytime Table 8-14.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.10 ATD Status Register 1 (ATDSTAT1) This read-only register contains the Conversion Complete Flags. Module Base + 0x000B R 7 6 5 4 3 2 1 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 8-12. ATD Status Register 1 (ATDSTAT1) Read: Anytime Write: Anytime, no effect Table 8-16.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.11 ATD Input Enable Register (ATDDIEN) Module Base + 0x000D 7 6 5 4 3 2 1 0 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 0 0 0 0 0 0 0 0 R W Reset Figure 8-13. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 8-17.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.12 Port Data Register (PORTAD) The data port associated with the ATD is general purpose I/O. The port pins are shared with the analog A/D inputs AN7–AN0. Module Base + 0x000F R 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 1 1 1 1 1 1 1 1 AN7 AN6 AN5 AN4 AN3‘ AN2 AN1 AN0 W Reset Pin Function = Unimplemented or Reserved Figure 8-14.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.13.1 Left Justified Result Data Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H 7 R BIT 9 MSB W BIT 7 MSB Reset 0 6 5 4 3 2 1 0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 0 0 0 0 0 0 0 10-bit data 8-bit data Figure 8-15.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.4 Functional Description The ATD10B8C is structured in an analog and a digital sub-block. 8.4.1 Analog Sub-block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 8.4.1.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.4.2 Digital Sub-block This subsection explains some of the digital features in more detail. See 7 for all details. 8.4.2.1 External Trigger Input (ETRIG) The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.4.2.2 General-Purpose Digital Port Operation The channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. Alternatively they can be configured as digital I/O signals with the port I/O data being held in PORTAD. The analog/digital multiplex operation is performed in the pads. The pad is always connected to the analog inputs of the ATD10B8C.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.5.1.3 Step 3 Configure how many conversions you want to perform in one sequence and define other settings in ATDCTL3. Example: Write S4C=1 to do 4 conversions per sequence. 8.5.1.4 Step 4 Configure resolution, sampling time and ATD clock speed in ATDCTL4. Example: Use default for resolution and sampling time by leaving SRES8, SMP1 and SMP0 clear. For a bus clock of 40MHz write 9 to PR4-0, this gives an ATD clock of 0.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.7 Interrupts The interrupt requested by the ATD10B8C is listed in Table 8-20. Refer to MCU specification for related vector address and priority. Table 8-20. ATD10B8C Interrupt Vectors Interrupt Source Sequence complete interrupt CCR Mask Local Enable I bit ASCIE in ATDCTL2 See Section 8.3.2, “Register Descriptions” for further details. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 250 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.1 Introduction This specification describes the function of the clocks and reset generator (CRGV4). 9.1.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Voltage Regulator Power-on Reset Low Voltage Reset 1 CRG RESET CM fail Clock Monitor OSCCLK EXTAL Oscillator XTAL COP Timeout XCLKS Reset Generator Clock Quality Checker COP RTI System Reset Bus Clock Core Clock Oscillator Clock Registers XFC VDDPLL VSSPLL PLLCLK PLL Clock and Reset Control Real-Time Interrupt PLL Lock Interrupt Self-Clock Mode Interrupt 1 Refer to the device overview section for availability of the low-volta
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description VDDPLL CS CP MCU RS XFC Figure 9-2. PLL Loop Filter Connections 9.2.3 RESET — Reset Pin RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered. 9.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the CRGV4.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description NOTE Register address = base address + address offset, where the base address is defined at the MCU level and the address offset is defined at the module level. 9.3.2 Register Descriptions This section describes in address order all the CRGV4 registers and their individual bits.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Register Name 0x000B ARMCOP Bit 7 6 5 4 3 2 1 Bit 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 = Unimplemented or Reserved Figure 9-3. CRG Register Summary (continued) 9.3.2.1 CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the PLL.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.2 CRG Reference Divider Register (REFDV) The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV + 1. Module Base + 0x0001 R 7 6 5 4 0 0 0 0 3 2 1 0 REFDV3 REFDV2 REFDV1 REFDV0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 9-5.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.4 CRG Flags Register (CRGFLG) This register provides CRG status bits and flags. Module Base + 0x0003 7 6 5 4 RTIF PORF LVRF LOCKIF 0 Note 1 Note 2 0 R 3 2 LOCK TRACK 1 0 SCM SCMIF W Reset 0 0 0 0 1. PORF is set to 1 when a power-on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset. = Unimplemented or Reserved Figure 9-7.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-2. CRGFLG Field Descriptions (continued) Field 1 SCMIF 0 SCM 9.3.2.5 Description Self-Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request. 0 No change in SCM bit. 1 SCM bit has changed. Self-Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.6 CRG Clock Select Register (CLKSEL) This register controls CRG clock selection. Refer to Figure 9-17 for details on the effect of each bit. Module Base + 0x0005 7 6 5 4 3 2 1 0 PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI 0 0 0 0 0 0 0 0 R W Reset Figure 9-9. CRG Clock Select Register (CLKSEL) Read: anytime Write: refer to each bit for individual write conditions Table 9-4.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-4. CLKSEL Field Descriptions (continued) Field 2 CWAI Description Core Stops in Wait Mode Bit — Write: anytime 0 Core clock keeps running in wait mode. 1 Core clock stops in wait mode. 1 RTIWAI RTI Stops in Wait Mode Bit — Write: anytime 0 RTI keeps running in wait mode. 1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-5. PLLCTL Field Descriptions (continued) Field Description 5 AUTO Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime except when PLLWAI=1, because PLLWAI sets the AUTO bit to 1. 0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-6. RTICTL Field Descriptions Field Description 6:4 RTR[6:4] Real-Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 9-7. 3:0 RTR[3:0] Real-Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional granularity. Table 9-7 shows all possible divide values selectable by the RTICTL register.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.9 CRG COP Control Register (COPCTL) This register controls the COP (computer operating properly) watchdog. Module Base + 0x0008 7 6 WCOP RSBCK 0 0 R 5 4 3 0 0 0 2 1 0 CR2 CR1 CR0 0 0 0 W Reset 0 0 0 = Unimplemented or Reserved Read: anytime Figure 9-12. CRG COP Control Register (COPCTL) Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode Write: RSBCK: once Table 9-8.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG’s functionality. Module Base + 0x0009 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 9-13.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. Module Base + 0x000B 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Reset Figure 9-15. ARMCOP Register Diagram Read: always reads 0x0000 Write: anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. The PLL can change between acquisition and tracking modes either automatically or manually. The VCO has a minimum operating frequency, which corresponds to the self-clock mode frequency fSCM.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description The PLL filter can be manually or automatically configured into one of two possible operating modes: • Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.4.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases. CORE CLOCK: BUS CLOCK / ECLK Figure 9-18. Core Clock and Bus Clock Relationship 9.4.3 Clock Monitor (CM) If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description The sequence for clock quality check is shown in Figure 9-20. CM fail Clock OK POR LVR exit full stop Clock Monitor Reset Enter SCM yes check window SCM active? num=num+1 yes osc ok num=50 no num=0 no ? num<50 ? yes no SCME=1 ? no yes SCM active? yes Switch to OSCCLK no Exit SCM Figure 9-20.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.4.5 Computer Operating Properly Watchdog (COP) WAIT(COPWAI), STOP(PSTP,PCE), COP enable CR[2:0] 0:0:0 CR[2:0] 0:0:1 ÷ 16384 OSCCLK gating condition = Clock Gate ÷4 0:1:0 ÷4 0:1:1 ÷4 1:0:0 ÷4 1:0:1 ÷2 1:1:0 ÷2 1:1:1 COP TIMEOUT Figure 9-21. Clock Chain for COP The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. The COP is disabled out of reset.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description If the PRE bit is set, the RTI will continue to run in pseudo-stop mode. . WAIT(RTIWAI), STOP(PSTP,PRE), RTI enable ÷ 1024 OSCCLK RTR[6:4] 0:0:0 0:0:1 ÷2 0:1:0 ÷2 0:1:1 ÷2 1:0:0 ÷2 1:0:1 ÷2 1:1:0 ÷2 1:1:1 gating condition = Clock Gate 4-BIT MODULUS COUNTER (RTR[3:0]) RTI TIMEOUT Figure 9-22. Clock Chain for RTI 9.4.7 9.4.7.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description NOTE In order to detect a potential clock loss, the CME bit should be always enabled (CME=1). If CME bit is disabled and the MCU is configured to run on PLL clock (PLLCLK), a loss of external clock (OSCCLK) will not be detected and will cause the system clock to drift towards the VCO’s minimum frequency fSCM. As soon as the external clock is available again the system clock ramps up to its PLL target frequency.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Core req’s Wait Mode. PLLWAI=1 ? no yes Clear PLLSEL, Disable PLL CWAI or SYSWAI=1 ? no yes Disable core clocks SYSWAI=1 ? no yes Disable system clocks no Enter Wait Mode CME=1 ? Wait Mode left due to external reset no yes Exit Wait w. ext.RESET CM fail ? INT ? yes no yes Exit Wait w.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description There are five different scenarios for the CRG to restart the MCU from wait mode: • External reset • Clock monitor reset • COP reset • Self-clock mode interrupt • Real-time interrupt (RTI) If the MCU gets an external reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-11. Outcome of Clock Loss in Wait Mode CME SCME SCMIE CRG Actions 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 1 1 0 Clock failure --> Scenario 1: OSCCLK recovers prior to exiting Wait Mode. – MCU remains in Wait Mode, – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – Set SCMIF interrupt flag.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-11. Outcome of Clock Loss in Wait Mode (continued) CME SCME SCMIE 1 1 1 CRG Actions Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. – Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. 9.4.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Core req’s Stop Mode. Clear PLLSEL, Disable PLL Exit Stop w. ext.RESET no Wait Mode left due to external INT ? no Enter Stop Mode PSTP=1 ? yes CME=1 ? yes no Exit Stop w. CMRESET no SCME=1 ? no yes Clock OK ? CM fail ? INT ? no yes no yes yes Exit Stop w.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description If the MCU gets an external reset during pseudo-stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Pseudo-stop mode is exited and the MCU is in run mode again.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-12. Outcome of Clock Loss in Pseudo-Stop Mode CME SCME SCMIE CRG Actions 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 1 1 0 Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-12. Outcome of Clock Loss in Pseudo-Stop Mode (continued) CME SCME SCMIE 1 1 1 CRG Actions Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. – Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. 9.4.10.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Definition.” All reset sources are listed in Table 9-13. Refer to the device overview chapter for related vector addresses and priorities. Table 9-13.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector. 9.5.
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in Table 9-15. Refer to the device overview chapter for related vector addresses and priorities. Table 9-15. CRG Interrupt Vectors 9.6.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.1 Introduction Freescale’s scalable controller area network (S12MSCANV2) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.1.2 Block Diagram MSCAN Oscillator Clock Bus Clock CANCLK MUX Presc. Tq Clk Receive/ Transmit Engine RXCAN TXCAN Transmit Interrupt Req. Receive Interrupt Req. Errors Interrupt Req. Message Filtering and Buffering Control and Status Wake-Up Interrupt Req. Configuration Registers Wake-Up Low Pass Filter Figure 10-1. MSCAN Block Diagram 10.1.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.1.4 Modes of Operation The following modes of operation are specific to the MSCAN. See Section 10.4, “Functional Description,” for details. • Listen-Only Mode • MSCAN Sleep Mode • MSCAN Initialization Mode • MSCAN Power Down Mode 10.2 External Signal Description The MSCAN uses two external pins: 10.2.1 RXCAN — CAN Receiver Input Pin RXCAN is the MSCAN receiver input pin. 10.2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MSCAN. 10.3.1 Module Memory Map Figure 10-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Register Name Bit 7 0x0000 CANCTL0 R 0x0001 CANCTL1 R W R 0x0003 CANBTR1 R 0x0004 CANRFLG R 0x0005 CANRIER R 0x0006 CANTFLG R W 0x0007 CANTIER W 0x0009 CANTAAK 0x000A CANTBSEL 0x000B CANIDAC 5 RXACT CSWAI 4 SYNCH 3 2 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 WUPIF CS
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Register Name 0x0010–0x0013 CANIDAR0–3 R 0x0014–0x0017 CANIDMRx R 0x0018–0x001B CANIDAR4–7 R 0x001C–0x001F CANIDMR4–7 R 0x0020–0x002F CANRXFG R 0x0030–0x003F CANTXFG R W W W W Bit 7 6 5 4 3 2 1 Bit 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 See Section 10.3.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-1. CANCTL0 Register Field Descriptions (continued) Field Description 1 SLPRQ(5) Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 10.4.5.4, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x0001 7 6 5 4 3 CANE CLKSRC LOOPB LISTEN 0 0 0 1 2 R 1 0 SLPAK INITAK 0 1 WUPM W Reset: 0 0 = Unimplemented Figure 10-5. MSCAN Control Register 1 (CANCTL1) Read: Anytime Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). Table 10-2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-2. CANCTL1 Register Field Descriptions (continued) Field Description 1 SLPAK Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Section 10.4.5.4, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0) The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module. Module Base + 0x0002 7 6 5 4 3 2 1 0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0 0 0 0 0 0 0 0 R W Reset: Figure 10-6. MSCAN Bus Timing Register 0 (CANBTR0) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-3.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module. Module Base + 0x0003 7 6 5 4 3 2 1 0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0 0 0 0 0 0 0 0 R W Reset: Figure 10-7. MSCAN Bus Timing Register 1 (CANBTR1) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-6.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-8. Time Segment 1 Values TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 0 0 1 Tq clock cycle(1) 0 0 0 1 2 Tq clock cycles1 0 0 1 0 3 Tq clock cycles1 0 0 1 1 4 Tq clock cycles : : : : : 1 1 1 0 15 Tq clock cycles 1 1 1 1 16 Tq clock cycles 1. This setting is not valid. Please refer to Table 10-34 for valid settings.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-9. CANRFLG Register Field Descriptions Field Description 7 WUPIF Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 10.4.5.4, “MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER) This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register. Module Base + 0x0005 7 6 5 4 3 2 1 0 WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE 0 0 0 0 0 0 0 0 R W Reset: Figure 10-9.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-10. CANRIER Register Field Descriptions (continued) Field Description 1 OVRIE Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. 0 RXFIE Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request. 1.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-11. CANTFLG Register Field Descriptions Field Description 2:0 TXE[2:0] Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ) The CANTARQ register allows abort request of queued messages as described below. Module Base + 0x0008 R 7 6 5 4 3 0 0 0 0 0 2 1 0 ABTRQ2 ABTRQ1 ABTRQ0 0 0 0 W Reset: 0 0 0 0 0 = Unimplemented Figure 10-12.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. Module Base + 0x0009 R 7 6 5 4 3 2 1 0 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 10-13.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL) The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space. Module Base + 0x000A R 7 6 5 4 3 0 0 0 0 0 2 1 0 TX2 TX1 TX0 0 0 0 W Reset: 0 0 0 0 0 = Unimplemented Figure 10-14.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC) The CANIDAC register is used for identifier acceptance control as described below. Module Base + 0x000B R 7 6 0 0 5 4 IDAM1 IDAM0 0 0 3 2 1 0 0 IDHIT2 IDHIT1 IDHIT0 0 0 0 0 W Reset: 0 0 = Unimplemented Figure 10-15.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well. 10.3.2.13 MSCAN Reserved Registers These registers are reserved for factory testing of the MSCAN module and is not available in normal system operation modes.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. 10.3.2.15 MSCAN Transmit Error Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.16 MSCAN Identifier Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 10.3.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x0018 (CANIDAR4) 0x0019 (CANIDAR5) 0x001A (CANIDAR6) 0x001B (CANIDAR7) R W Reset R W Reset R W Reset R W Reset 7 6 5 4 3 2 1 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AC7 AC6 AC5 AC4 AC3
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.17 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x001C (CANIDMR4) 0x001D (CANIDMR5) 0x001E (CANIDMR6) 0x001F (CANIDMR7) R W Reset R W Reset R W Reset R W Reset 7 6 5 4 3 2 1 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 AM7 AM6 AM5 AM4 AM3
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.3 Programmer’s Model of Message Storage The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Register Name 0x00X0 IDR0 0x00X1 IDR1 R W R W R 0x00X2 IDR2 W 0x00X3 IDR3 W 0x00X4 DSR0 0x00X5 DSR1 R R W R W R 0x00X6 DSR2 W 0x00X7 DSR3 W 0x00X8 DSR4 R R W R 0x00X9 DSR5 W 0x00XA DSR6 W 0x00XB DSR7 0x00XC DLR R R W Bit 7 6 5 4 3 2 1 Bit0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Write: For transmit buffers, anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for receive buffers.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x00X1 7 6 5 4 3 2 1 0 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 x x x x x x x x R W Reset: Figure 10-26. Identifier Register 1 (IDR1) — Extended Identifier Mapping Table 10-25. IDR1 Register Field Descriptions — Extended Field Description 7:5 ID[20:18] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x00X3 7 6 5 4 3 2 1 0 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR x x x x x x x x R W Reset: Figure 10-28. Identifier Register 3 (IDR3) — Extended Identifier Mapping Table 10-27. IDR3 Register Field Descriptions — Extended Field Description 7:1 ID[6:0] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x00X1 7 6 5 4 3 ID2 ID1 ID0 RTR IDE (=0) x x x x x 2 1 0 x x x R W Reset: = Unused; always read ‘x’ Figure 10-30. Identifier Register 1 — Standard Mapping Table 10-29. IDR1 Register Field Descriptions Field Description 7:5 ID[2:0] Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x00X3 7 6 5 4 3 2 1 0 x x x x x x x x R W Reset: = Unused; always read ‘x’ Figure 10-32. Identifier Register 3 — Standard Mapping 10.3.3.2 Data Segment Registers (DSR0-7) The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.3.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. Module Base + 0x00XB 7 6 5 4 3 2 1 0 DLC3 DLC2 DLC1 DLC0 x x x x R W Reset: x x x x = Unused; always read “x” Figure 10-34. Data Length Register (DLR) — Extended Identifier Mapping Table 10-31.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. Module Base + 0xXXXD 7 6 5 4 3 2 1 0 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 0 0 0 0 0 0 0 0 R W Reset: Figure 10-35. Transmit Buffer Priority Register (TBPR) Read: Anytime when TXEx flag is set (see Section 10.3.2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Read: Anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Unimplemented 10.4 10.4.1 Functional Description General This section provides a complete functional description of the MSCAN.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.2 Message Storage CAN Receive / Transmit Engine CPU12 Memory Mapped I/O Rx0 RXF Receiver TxBG Tx0 MSCAN TxFG Tx1 TxBG Tx2 Transmitter CPU bus RxFG RxBG MSCAN Rx1 Rx2 Rx3 Rx4 TXE0 PRIO TXE1 CPU bus PRIO TXE2 PRIO Figure 10-38. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 10.4.7.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) • • — a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or — b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 10-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDA3, CANIDMR0–3CANIDMR) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 2 and 3 hits.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID15 IDE ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDR2 ID3 ID10 IDR3 ID3 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure 10-40.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-33. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this period. SYNC_SEG Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.4.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification. 10.4.4.4 Listen-Only Mode In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a transmision.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-35. CPU vs. MSCAN Operating Modes MSCAN Mode Reduced Power Consumption CPU Mode Normal Sleep RUN CSWAI = X(1) SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = 1 SLPAK = 1 WAIT CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 1 SLPAK = 1 STOP Power Down Disabled (CANE=0) CSWAI = X SLPRQ = X SLPAK = X CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X 1.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) • • • If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) The MSCAN is able to leave sleep mode (wake up) only when: • CAN bus activity occurs and WUPE = 1 or • the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.5.5 MSCAN Initialization Mode In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.5.6 MSCAN Power Down Mode The MSCAN is in power down mode (Table 10-35) when • CPU is in stop mode or • CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.7.1 Description of Interrupt Operation The MSCAN supports four interrupt vectors (see Table 10-36), any of which can be individually masked (for details see sections from Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER),” to Section 10.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”). NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter. Table 10-36.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) “MSCAN Receiver Flag Register (CANRFLG)” and Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). 10.4.7.6 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either the Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” or the Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG).” Interrupts are pending as long as one of the corresponding flags is set.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 342 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 11 Oscillator (OSCV2) Block Description 11.1 Introduction The OSCV2 module provides two alternative oscillator concepts: • A low noise and low power Colpitts oscillator with amplitude limitation control (ALC) • A robust full swing Pierce oscillator with the possibility to feed in an external square wave 11.1.
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Chapter 11 Oscillator (OSCV2) Block Description 11.2 External Signal Description This section lists and describes the signals that connect off chip. 11.2.1 VDDPLL and VSSPLL — PLL Operating Voltage, PLL Ground These pins provide the operating voltage (VDDPLL) and ground (VSSPLL) for the OSCV2 circuitry. This allows the supply voltage to the OSCV2 to be independently bypassed. 11.2.
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Chapter 11 Oscillator (OSCV2) Block Description EXTAL MCU RB C3 Crystal or Ceramic Resonator RS* XTAL C4 VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer’s data. Figure 11-2. Pierce Oscillator Connections (XCLKS = 1) EXTAL CMOS-Compatible External Oscillator (VDDPLL Level) MCU XTAL Not Connected Figure 11-3. External Clock Connections (XCLKS = 1) 11.2.
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Chapter 11 Oscillator (OSCV2) Block Description 11.3 Memory Map and Register Definition The CRG contains the registers and associated bits for controlling and monitoring the OSCV2 module. 11.4 Functional Description The OSCV2 block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.1 Introduction The pulse width modulation (PWM) definition is based on the HC12 PWM definitions. The PWM8B6CV1 module contains the basic features from the HC11 with some of the enhancements incorporated on the HC12, that is center aligned output mode and four available clock sources. The PWM8B6CV1 module has six channels with independent control of left and center aligned outputs on each channel.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.1.3 Block Diagram PWM8B6C PWM Channels Channel 5 Bus Clock Clock Select PWM Clock Period and Duty PWM5 Counter Channel 4 Period and Duty PWM4 Counter Control Channel 3 Period and Duty PWM3 Counter Channel 2 Enable Period and Duty PWM2 Counter Channel 1 Polarity Period and Duty Alignment PWM1 Counter Channel 0 Period and Duty PWM0 Counter Figure 12-1. PWM8B6CV1 Block Diagram 12.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.2.4 PWM2 — Pulse Width Modulator Channel 2 Pin This pin serves as waveform output of PWM channel 2. 12.2.5 PWM1 — Pulse Width Modulator Channel 1 Pin This pin serves as waveform output of PWM channel 1. 12.2.6 PWM0 — Pulse Width Modulator Channel 0 Pin This pin serves as waveform output of PWM channel 0. 12.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-1.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2 Register Descriptions The following paragraphs describe in detail all the registers and register bits in the PWM8B6CV1 module.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x000F PWMCNT3 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0x0010 PWMCNT4 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0x0011 PWMCNT5 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0x0012 PWMPER0 R W Bit 7 6 5 4 3 2 1 Bit 0 0x0013 PWMPER1 R W Bit 7 6 5 4 3 2 1 Bit 0 0x0014 PWMPER2 R W Bit 7 6 5 4 3 2 1 Bit 0 0x0015 PWMPER3 R W Bit 7 6 5 4
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-2. PWME Field Descriptions (continued) Field Description 1 PWME1 Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. 0 PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-3. PWMPOL Field Descriptions (continued) Field Description 3 PPOL3 Pulse Width Channel 3 Polarity 0 PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-4. PWMCLK Field Descriptions Field Description 5 PCLK5 Pulse Width Channel 5 Clock Select 0 Clock A is the clock source for PWM channel 5. 1 Clock SA is the clock source for PWM channel 5. 4 PCLK4 Pulse Width Channel 4 Clock Select 0 Clock A is the clock source for PWM channel 4. 1 Clock SA is the clock source for PWM channel 4. 3 PCLK3 Pulse Width Channel 3 Clock Select 0 Clock B is the clock source for PWM channel 3.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-5. PWMPRCLK Field Descriptions Field Description 6:5 PCKB[2:0] Prescaler Select for Clock B — Clock B is 1 of two clock sources which can be used for channels 2 or 3. These three bits determine the rate of clock B, as shown in Table 12-6. 2:0 PCKA[2:0] Prescaler Select for Clock A — Clock A is 1 of two clock sources which can be used for channels 0, 1, 4, or 5.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x0004 R 7 6 0 0 5 4 3 2 1 0 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 0 0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 12-7. PWM Center Align Enable Register (PWMCAE) Read: anytime Write: anytime NOTE Write these bits only when the corresponding channel is disabled. Table 12-8.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x0005 7 R 6 5 4 3 2 CON45 CON23 CON01 PSWAI PFRZ 0 0 0 0 0 0 1 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 12-8. PWM Control Register (PWMCTL) Read: anytime Write: anytime There are three control bits for concatenation, each of which is used to concatenate a pair of PWM channels into one 16-bit channel.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-9. PWMCTL Field Descriptions Field Description 6 CON45 Concatenate Channels 4 and 5 0 Channels 4 and 5 are separate 8-bit PWMs. 1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high-order byte and channel 5 becomes the low-order byte. Channel 5 output pin is used as the output for this 16-bit PWM (bit 5 of port PWMP).
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.7 Reserved Register (PWMTST) This register is reserved for factory testing of the PWM module and is not available in normal modes. Module Base + 0x0006 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-9.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.9 PWM Scale A Register (PWMSCLA) PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) NOTE When PWMSCLA = 0x0000, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.11 Reserved Registers (PWMSCNTx) The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are not available in normal modes. Module Base + 0x000A R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-13.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.12 PWM Channel Counter Registers (PWMCNTx) Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register – 1.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x000E 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 12-17. PWM Channel Counter Registers (PWMCNT2) Module Base + 0x000F 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 12-18.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description • The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x0015 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 12-24. PWM Channel Period Registers (PWMPER3) Module Base + 0x0016 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 12-25.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. Reference Section 12.4.2.3, “PWM Period and Duty,” for more information. NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x001B 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 R W Reset Figure 12-30. PWM Channel Duty Registers (PWMDTY3) Module Base + 0x001C 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 R W Reset Figure 12-31.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-10. PWMSDN Field Descriptions Field Description 7 PWMIF PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will be flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect. 0 No change on PWM5IN input. 1 Change on PWM5IN input 6 PWMIE PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4 Functional Description 12.4.1 PWM Clock Select There are four available clocks called clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Clock A M U X Clock to PWM Ch 0 Clock A/2, A/4, A/6,....A/512 PCKA2 PCKA1 PCKA0 PCLK0 8-Bit Down Counter Count = 1 M U X Load PWMSCLA Clock SA DIV 2 PCLK1 M U X M Clock to PWM Ch 1 Clock to PWM Ch 2 U PCLK2 8 16 32 64 128 M U X Clock B 4 M U X Clock to PWM Ch 4 Clock B/2, B/4, B/6,....
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.1.2 Clock Scale The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.1.3 Clock Select Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For channels 2 and 3 the choices are clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. 12.4.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.2.1 PWM Enable Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are concatenated.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.2.4 PWM Timer Counters Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (reference Figure 12-34 for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 12-35. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.2.5 Left Aligned Outputs The PWM timer provides the choice of two types of outputs, left aligned or center aligned outputs. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is configured as an up counter only.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Shown below is the output waveform generated. E = 100 ns DUTY CYCLE = 75% PERIOD = 400 ns Figure 12-37. PWM Left Aligned Output Example Waveform 12.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Clock Source 5 High Low PWMCNT4 PWCNT5 Period/Duty Compare PWM5 Clock Source 3 High Low PWMCNT2 PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High Low PWMCNT0 PWCNT1 Period/Duty Compare PWM1 Figure 12-40. PWM 16-Bit Mode When using the 16-bit concatenated mode, the clock source is determined by the low-order 8-bit channel clock select control bits.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-12 is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 12-12. 16-bit Concatenation Mode Summary 12.4.2.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 382 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.1 Introduction This block guide provide an overview of serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs. 13.1.1 Glossary IRQ — Interrupt Request LSB — Least Significant Bit MSB — Most Significant Bit NRZ — Non-Return-to-Zero RZI — Return-to-Zero-Inverted RXD — Receive Pin SCI — Serial Communication Interface TXD — Transmit Pin 13.1.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description • • • — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection 13.1.3 Modes of Operation The SCI operation is the same independent of device resource mapping and bus interface mode. Different power modes are available to facilitate power saving. 13.1.3.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.1.4 Block Diagram Figure 13-1 is a high level block diagram of the SCI module, showing the interaction of various functional blocks.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3 Memory Map and Registers This section provides a detailed description of all memory and registers. 13.3.1 Module Memory Map The memory map for the SCI module is given below in Figure 13-2. The Address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3.2.1 SCI Baud Rate Registers (SCIBDH and SCHBDL) Module Base + 0x_0000 R 7 6 5 0 0 0 4 3 2 1 0 SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 0 0 0 0 1 0 0 Module Base + 0x_0001 R W Reset = Unimplemented or Reserved Figure 13-3.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3.2.2 SCI Control Register 1 (SCICR1) Module Base + 0x_0002 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 R W Reset Figure 13-4. SCI Control Register 1 (SCICR1) Read: Anytime Write: Anytime Table 13-2. SCICR1 Field Descriptions Field Description 7 LOOPS Loop Select Bit — LOOPS enables loop operation.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Table 13-3. Loop Functions 13.3.2.3 LOOPS RSRC Function 0 x Normal operation 1 0 Loop mode with Rx input internally connected to Tx output 1 1 Single-wire mode with Rx input connected to TXD SCI Control Register 2 (SCICR2) Module Base + 0x_0003 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 R W Reset Figure 13-5.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Table 13-4. SCICR2 Field Descriptions (continued) Field Description 1 RWU Receiver Wakeup Bit — Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. 0 SBK Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set).
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Table 13-5. SCISR1 Field Descriptions (continued) Field Description 5 RDRF Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL).
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3.2.5 SCI Status Register 2 (SCISR2) Module Base + 0x_0005 R 7 6 5 4 3 0 0 0 0 0 2 1 BK13 TXDIR 0 0 0 RAF W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-7. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime; writing accesses SCI status register 2; writing to any bits except TXDIR and BRK13 (SCISR2[1] & [2]) has no effect Table 13-6.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3.2.6 SCI Data Registers (SCIDRH and SCIDRL) Module Base + 0x_0006 7 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 R 6 R8 T8 W Reset 0 Module Base + 0x_0007 Reset = Unimplemented or Reserved Figure 13-8.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 13-9 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, NRZ serial communication between the CPU and remote devices, including other CPUs.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.1 Data Format The SCI uses the standard NRZ mark/space data format illustrated in Figure 13-10 below. PARITY OR DATA BIT 8-BIT DATA FORMAT BIT M IN SCICR1 CLEAR START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 PARITY OR DATA BIT 9-BIT DATA FORMAT BIT M IN SCICR1 SET START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 NEXT START BIT STOP BIT BIT 6 BIT 7 STOP BIT BIT 8 NEXT START BIT Figure 13-10.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.2 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12–SBR0 bits determines the module clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.3 Transmitter INTERNAL BUS BUS CLOCK ÷ 16 BAUD DIVIDER SCI DATA REGISTERS 11-BIT TRANSMIT SHIFT REGISTER H 8 7 6 5 4 3 2 1 0 TXD L PARITY GENERATION LOOP CONTROL BREAK (ALL 0s) PT SHIFT ENABLE PE LOAD FROM SCIDR T8 PREAMBLE (ALL ONES) MSB M START STOP SBR12–SBR0 TO RXD LOOPS RSRC TRANSMITTER CONTROL TDRE INTERRUPT REQUEST TC INTERRUPT REQUEST TDRE TE SBK TIE TC TCIE Figure 13-11.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIBDH has no effect without also writing to SCIBDL.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the Tx output signal. Setting TE after the stop bit appears on Tx output signal causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.4.2 Character Reception During an SCI reception, the receive shift register shifts a frame in from the Rx input signal. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Table 13-11. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-12 summarizes the results of the data bit samples. Table 13-12.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description In Figure 13-14 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description In Figure 13-16, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Figure 13-18 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.4.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. 13.4.4.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description With the misaligned character shown in Figure 13-20, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% 13.4.4.5.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup. 13.4.4.6.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.5 Single-Wire Operation Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. TRANSMITTER Tx OUTPUT SIGNAL Tx INPUT SIGNAL RECEIVER RXD Figure 13-22.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.5.2 13.5.2.1 Interrupt Operation System Level Interrupt Sources There are five interrupt sources that can generate an SCI interrupt in to the CPU. They are listed in Table 13-14. Table 13-14. SCI Interrupt Source Interrupt Source Flag Local Enable Transmitter TDRE TIE Transmitter TC TCIE Receiver RDRF RIE Receiver IDLE OR 410 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.5.2.2 Interrupt Descriptions The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent.
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 412 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 14.1.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.1.3 Block Diagram Figure 14-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control, and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.2.2 MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. 14.2.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Table 14-2. SPICR1 Field Descriptions Field Description 7 SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. 6 SPE SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.3.2.2 SPI Control Register 2 (SPICR2) Module Base 0x0001 R 7 6 5 0 0 0 4 3 MODFEN BIDIROE 0 0 2 1 0 SPISWAI SPC0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 14-4. SPI Control Register 2 (SPICR2) Read: anytime Write: anytime; writes to the reserved bits have no effect Table 14-4.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Table 14-5. Bidirectional Pin Configurations (continued) Pin Mode SPC0 BIDIROE MISO MOSI Bidirectional 1 0 Slave In MOSI not used by SPI 1 Slave I/O 14.3.2.3 SPI Baud Rate Register (SPIBR) Module Base 0x0002 7 R 6 5 4 3 SPPR2 SPPR1 SPPR0 0 0 0 0 2 1 0 SPR2 SPR1 SPR0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 14-5.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Table 14-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) 420 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 0 0 0 0 2 12.5 MHz 0 0 0 0 0 1 4 6.25 MHz 0 0 0 0 1 0 8 3.125 MHz 0 0 0 0 1 1 16 1.5625 MHz 0 0 0 1 0 0 32 781.25 kHz 0 0 0 1 0 1 64 390.63 kHz 0 0 0 1 1 0 128 195.31 kHz 0 0 0 1 1 1 256 97.66 kHz 0 0 1 0 0 0 4 6.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Table 14-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 1 0 0 1 1 1 1280 19.53 kHz 1 0 1 0 0 0 12 2.08333 MHz 1 0 1 0 0 1 24 1.04167 MHz 1 0 1 0 1 0 48 520.83 kHz 1 0 1 0 1 1 96 260.42 kHz 1 0 1 1 0 0 192 130.21 kHz 1 0 1 1 0 1 384 65.10 kHz 1 0 1 1 1 0 768 32.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.3.2.4 SPI Status Register (SPISR) Module Base 0x0003 R 7 6 5 4 3 2 1 0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 14-6. SPI Status Register (SPISR) Read: anytime Write: has no effect Table 14-8. SPISR Field Descriptions Field Description 7 SPIF SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI Data Register.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Write: anytime The SPI Data Register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For a SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI Transmitter Empty Flag SPTEF in the SPISR register indicates when the SPI Data Register is ready to accept new data.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI Data Register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.4.2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear. • SCK Clock In slave mode, SCK is the SPI clock input from the master. • MISO and MOSI Pins In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2. • SS Pin The SS pin is the slave select input.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.4.3 Transmission Formats During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device, slave devices that are not selected do not interfere with SPI bus activities.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in. After the 16th (last) SCK edge: • Data that was previously in the master SPI Data Register should now be in the slave data register and the data that was in the slave data register should be in the master.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time. 14.4.3.3 CPHA = 1 Transfer Format Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description End of Idle State Begin SCK Edge Nr.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. BaudRateDivisor = ( SPPR + 1 ) • 2 ( SPR + 1 ) Figure 14-11. Baud Rate Divisor Equation 14.4.5 14.4.5.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. The SCK is output for the master mode and input for the slave mode. The SS is the input or output for the master mode, and it is always the input for the slave mode.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.4.7 Operation in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled. 14.4.8 Operation in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.5 Reset The reset values of registers and signals are described in the Memory Map and Registers section (see Section 14.3, “Memory Map and Register Definition”) which details the registers and their bit-fields. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset.
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 434 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Table 15-1. Revision History Version Number Revision Dates Effective Date Author 01.03 06 Feb 2006 06 Feb 2006 S. Chinnam Corrected the type at 0x006 and later in the document from TSCR2 and TSCR1 01.04 08 July 2008 08 July 2008 S. Chinnam Revised flag clearing procedure, whereby TEN bit must be set when clearing flags. 01.05 05 May 2010 05 May 2010 Ame Wang -in 15.3.2.8/15-446,add Table 15-11 -in 15.3.2.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.1.2 Modes of Operation Stop: Timer is off because clocks are stopped. Freeze: Timer counter keep on running, unless TSFRZ in TSCR (0x0006) is set to 1. Wait: Counters keep on running, unless TSWAI in TSCR (0x0006) is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR (0x0006) is cleared to 0. 15.1.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description TIMCLK (Timer clock) CLK1 CLK0 Intermodule Bus Clock select (PAMOD) Edge detector PT7 PACLK PACLK / 256 PACLK / 65536 Prescaled clock (PCLK) 4:1 MUX Interrupt PACNT MUX Divide by 64 M clock Figure 15-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer PTn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 15-3. Interrupt Flag Setting Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description PULSE ACCUMULATOR PAD CHANNEL 7 OUTPUT COMPARE OM7 OL7 OC7M7 Figure 15-4. Channel 7 Output Compare/Pulse Accumulator Logic NOTE For more information see the respective functional descriptions in Section 15.4, “Functional Description,” of this document. 15.2 External Signal Description The TIM16B8CV1 module has a total of eight external pins. 15.2.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin This pin serves as input capture or output compare for channel 2. 15.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin This pin serves as input capture or output compare for channel 1. 15.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin This pin serves as input capture or output compare for channel 0. NOTE For the description of interrupts see Section 15.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Table 15-2.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Register Name Bit 7 0x000D TSCR2 R W 0x000E TFLG1 R W 0x000F TFLG2 R W R 0x0010–0x001F TCxH–TCxL W R W 0x0020 PACTL R 6 5 4 3 2 1 Bit 0 0 0 0 TCRE PR2 PR1 PR0 C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 PAOVF PAIF PACNT15 PACNT14 PACN
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Write: Anytime Table 15-3. TIOS Field Descriptions Field 7:0 IOS[7:0] 15.3.2.2 Description Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture. 1 The corresponding channel acts as an output compare.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Table 15-5. OC7M Field Descriptions Field Description 7:0 OC7M[7:0] Output Compare 7 Mask — Setting the OC7Mx (x ranges from 0 to 6) will set the corresponding port to be an output port when the corresponding TIOSx (x ranges from 0 to 6) bit is set to be an output compare. Note: A successful channel 7 output compare overrides any channel 6:0 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit. 15.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read: Anytime Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1).
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Table 15-7. TSCR1 Field Descriptions (continued) Field Description 5 TSFRZ Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Module Base + 0x0009 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 R W Reset Figure 15-15. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime Table 15-9. TCTL1/TCTL2 Field Descriptions Field Description 7:0 OMx Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Note: in Table 15-11, the IOS7 and IOSx should be set to 1 IOSx is the register TIOS bit x, OC7Mx is the register OC7M bit x, TCx is timer Input Capture/Output Compare register, IOCx is channel x, OMx/OLx is the register TCTL1/TCTL2, OC7Dx is the register OC7D bit x. IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value. 448 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4) Module Base + 0x000A 7 6 5 4 3 2 1 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 R W Reset Figure 15-16. Timer Control Register 3 (TCTL3) Module Base + 0x000B 7 6 5 4 3 2 1 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0 0 0 0 0 0 0 0 R W Reset Figure 15-17.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.3.2.10 Timer Interrupt Enable Register (TIE) Module Base + 0x000C 7 6 5 4 3 2 1 0 C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 0 0 0 0 0 R W Reset Figure 15-18. Timer Interrupt Enable Register (TIE) Read: Anytime Write: Anytime. Table 15-14. TIE Field Descriptions Field Description 7:0 C7I:C0I Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Table 15-15. TSCR2 Field Descriptions Field 7 TOI Description Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set. 3 TCRE Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7 event. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset inhibited and counter free runs.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. Table 15-17. TRLG1 Field Descriptions Field 7:0 C[7:0]F Description Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output compare event occurs. Clearing requires writing a one to the corresponding flag bit when TEN is set to one.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0–7 (TCxH and TCxL) 0x0018 = TC4H 0x001A = TC5H 0x001C = TC6H 0x001E = TC7H Module Base + 0x0010 = TC0H 0x0012 = TC1H 0x0014 = TC2H 0x0016 = TC3H 15 14 13 12 11 10 9 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R W Reset Figure 15-22.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) Module Base + 0x0020 7 R 6 5 4 3 2 1 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 0 W Reset 0 Unimplemented or Reserved Figure 15-24. 16-Bit Pulse Accumulator Control Register (PACTL) When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7. Read: Any time Write: Any time Table 15-19.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Table 15-20. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div. by 64 clock enabled with pin high level 1 1 Div. by 64 clock enabled with pin low level NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the ÷64 clock is generated by the timer prescaler. Table 15-21.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Table 15-22. PAFLG Field Descriptions Field Description 1 PAOVF Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000. Clearing this bit requires wirting a one to this bit in the PAFLG register while TEN bit of TSCR1 register is set to one. 0 PAIF Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.3.2.17 Pulse Accumulators Count Registers (PACNT) Module Base + 0x0022 15 14 13 12 11 10 9 0 PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 0 0 0 0 0 0 0 0 R W Reset Figure 15-26. Pulse Accumulator Count Register High (PACNTH) Module Base + 0x0023 7 6 5 4 3 2 1 0 PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 0 0 0 0 0 0 0 0 R W Reset Figure 15-27.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Bus Clock CLK[1:0] PR[2:1:0] channel 7 output compare PACLK PACLK/256 PACLK/65536 MUX TCRE PRESCALER CxI TCNT(hi):TCNT(lo) CxF CLEAR COUNTER 16-BIT COUNTER TOF INTERRUPT LOGIC TOI TE TOF CHANNEL 0 16-BIT COMPARATOR OM:OL0 TC0 EDG0A C0F C0F EDGE DETECT EDG0B CH. 0 CAPTURE IOC0 PIN LOGIC CH. 0COMPARE TOV0 IOC0 PIN IOC0 CHANNEL 1 16-BIT COMPARATOR OM:OL1 EDGE DETECT EDG1B EDG1A C1F C1F TC1 CH. 1 CAPTURE IOC1 PIN LOGIC CH.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.4.2 Input Capture Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCx. The minimum pulse width for the input capture input is greater than two bus clocks.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description Note: in Figure 15-29,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock Figure 15-29. The TCNT cycle diagram under TCRE=1 condition prescaler counter TC7 1 bus clock 0 1 ----- TC7-1 0 TC7 event TC7 event 15.4.4 TC7 Pulse Accumulator The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes: Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, PAI.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.4.6 Gated Time Accumulation Mode Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE bit selects low levels or high levels to enable the divided-by-64 clock. The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to generate interrupt requests.
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Chapter 15 Timer Module (TIM16B8CV1) Block Description 15.6.2 Pulse Accumulator Input Interrupt (PAOVI) This active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller. 15.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) This active high output will be asserted by the module to request a timer pulse accumulator overflow interrupt to be serviced by the system controller. 15.6.
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Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.1 Introduction The VREG3V3V2 is a dual output voltage regulator providing two separate 2.5 V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3 V up to 5 V (typical). 16.1.
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Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.1.3 Block Diagram Figure 16-1 shows the function principle of VREG3V3V2 by means of a block diagram. The regulator core REG consists of two parallel sub-blocks, REG1 and REG2, providing two independent output voltages.
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Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.2 External Signal Description Due to the nature of VREG3V3V2 being a voltage regulator providing the chip internal power supply voltages most signals are power supply signals connected to pads. Table 16-1 shows all signals of VREG3V3V2 associated with pins. Table 16-1.
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Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.2.3 VDD, VSS — Regulator Output1 (Core Logic) Signals VDD/VSS are the primary outputs of VREG3V3V2 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In Shutdown Mode an external supply at VDD/VSS can replace the voltage regulator. 16.2.
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Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.3.2 Register Descriptions The following paragraphs describe, in address order, all the VREG3V3V2 registers and their individual bits. 16.3.2.1 VREG3V3V2 — Control Register (VREGCTRL) The VREGCTRL register allows to separately enable features of VREG3V3V2. Module Base + 0x0000 R 7 6 5 4 3 2 0 0 0 0 0 LVDS 1 0 LVIE LVIF 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 16-2.
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Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.4.1 REG — Regulator Core VREG3V3V2, respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only REG1 providing the supply at VDD/VSS is explained. The principle is also valid for REG2.
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Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.5 Resets This subsection describes how VREG3V3V2 controls the reset of the MCU.The reset values of registers and signals are provided in Section 16.3, “Memory Map and Register Definition”. Possible reset sources are listed in Table 16-4. Table 16-4. VREG3V3V2 — Reset Sources Reset Source 16.5.
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Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 470 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.1 Introduction The FTS16K module implements a 16 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 16 Kbytes organized as 256 rows of 64 bytes with an erase sector size of eight rows (512 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.1.3 Modes of Operation See Section 17.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 17.4.1, “Flash Command Operations”. 17.1.4 Block Diagram Figure 17-1 shows a block diagram of the FTS16K module.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.3 Memory Map and Registers This section describes the FTS16K memory map and registers. 17.3.1 Module Memory Map The FTS16K memory map is shown in Figure 17-2. The HCS12 architecture places the Flash array addresses between 0xC000 and 0xFFFF. The content of the HCS12 Core PPAGE register is used to map the logical page ranging from address 0x8000 to 0xBFFF to a physical 16K byte page in the Flash array memory.1 The FPROT register (see Section 17.3.2.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F 0x8000 16K PAGED Flash Array MEMORY 0x3F FLASH_START = 0xC000 0xE000 Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0x3F 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x3F corresponds to the PPAGE register content Figure 17-2. Flash Memory Map Table 17-2.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 17-3. Detailed descriptions of each register bit are provided.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 R 6 5 4 3 2 1 0 PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 0 0 0 0 0 0 0 FDIVLD W Reset 0 = Unimplemented or Reserved Figure 17-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) Table 17-4. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 17-5. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 17-6.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 CBEIE CCIE KEYACC 0 0 0 R 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-7. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to. A protected Flash sector is disabled by FPHDIS while the size of the protected sector is defined by FPHS[1:0] in the FPROT register.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) Figure 17-9 illustrates all possible protection scenarios. Although the protection scheme is loaded from the Flash array after reset, it is allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) Table 17-11. Flash Protection Scenario Transitions From Protection Scenario To Protection Scenario(1) 0 1 3 X X 1. Allowed transitions marked with X. 17.3.2.6 2 3 X X Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) Table 17-12. FSTAT Field Descriptions Field Description 5 PVIOL Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) Table 17-13. FCMD Field Descriptions Field Description 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Valid Flash commands are shown in Table 17-14. An attempt to execute any command other than those listed in Table 17-14 will set the ACCERR bit in the FSTAT register (see Section 17.3.2.6). Table 17-14. Valid Flash Command List CMDB 17.3.2.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) Module Base + 0x0009 7 6 5 4 3 2 1 0 0 0 0 0 R FABLO W Reset 0 0 0 0 Figure 17-14. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable. For sector erase, the MCU address bits [8:0] are ignored. For mass erase, any address within the Flash array is valid to start the command. 17.3.2.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-17. RESERVED3 All bits read 0 and are not writable. 17.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-18.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-20. RESERVED6 All bits read 0 and are not writable. 17.4 Functional Description 17.4.1 Flash Command Operations Write operations are used for the program, erase, and erase verify algorithms described in this section.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 17-21. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.4.1.3 Valid Flash Commands Table 17-15 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 17-15. Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 17-22. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Array Address and Dummy Data 2. Write: FCMD register Erase Verify Command 0x05 3.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 17-23. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Address and program Data 2. Write: FCMD register Program Command 0x20 3.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 512 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 17-24. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Sector Address and Dummy Data 2. Write: FCMD register Sector Erase Command 0x40 3.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 17-25. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Block Address and Dummy Data 2. Write: FCMD register Mass Erase Command 0x41 3.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.4.1.4 17.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.4.2 17.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 17.4.5). 17.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
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Chapter 17 16 Kbyte Flash Module (S12FTS16KV1) 17.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 17-1: • FPROT — Flash Protection Register (see Section 17.3.2.5) • FSEC — Flash Security Register (see Section 17.3.2.2) 17.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.1 Introduction The FTS32K module implements a 32 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 32 Kbytes organized as 512 rows of 64 bytes with an erase sector size of eight rows (512 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.1.3 Modes of Operation See Section 18.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 18.4.1, “Flash Command Operations”. 18.1.4 Block Diagram Figure 18-1 shows a block diagram of the FTS32K module.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.3 Memory Map and Registers This section describes the FTS32K memory map and registers. 18.3.1 Module Memory Map The FTS32K memory map is shown in Figure 18-2. The HCS12 architecture places the Flash array addresses between 0x4000 and 0xFFFF, which corresponds to three 16 Kbyte pages.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH_START = 0x4000 0x4200 0x4400 Flash Protected Low Sectors 512 bytes, 1, 2, 4 Kbytes 0x4800 0x5000 0x3E Flash Array 0x8000 16K PAGED MEMORY 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x3E–0x3F correspond to the PPAGE register content Figure 18-2.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) Table 18-2. Flash Array Memory Map Summary MCU Address Range 0x4000–0x7FFF PPAGE Unpaged (0x3E) Protectable Low Range Protectable High Range Array Relative Address(1) 0x4000–0x43FF N.A. 0x18000–0x1BFFF N.A. 0x18000–0x1BFFF 0xB800–0xBFFF 0x1C000–0x1FFFF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x3E 0x8000–0x83FF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 18-3. Detailed descriptions of each register bit are provided.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 R 6 5 4 3 2 1 0 PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 0 0 0 0 0 0 0 FDIVLD W Reset 0 = Unimplemented or Reserved Figure 18-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) Table 18-4. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 18-5. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 18-6.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 CBEIE CCIE KEYACC 0 0 0 R 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-7. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 18-8. To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) Table 18-9.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPHS[1:0] FPOPEN = 1 Scenario FPLS[1:0] FPHDIS = 1 FPLDIS = 1 FPHS[1:0] FPOPEN = 0 Scenario FPLS[1:0] 0xFFFF 0xFFFF Protected Flash Figure 18-9. Flash Protection Scenarios 18.3.2.5.1 Flash Protection Restrictions The general guideline is that protection can only be added, not removed.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) Table 18-12. Flash Protection Scenario Transitions To Protection Scenario(1) From Protection Scenario 0 1 6 X 7 X X 1. Allowed transitions marked with X. 18.3.2.6 2 X 3 4 X X X X 5 6 7 X X X X Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) Table 18-13. FSTAT Field Descriptions Field Description 5 PVIOL Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) Table 18-14. FCMD Field Descriptions Field Description 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Valid Flash commands are shown in Table 18-15. An attempt to execute any command other than those listed in Table 18-15 will set the ACCERR bit in the FSTAT register (see Section 18.3.2.6). Table 18-15. Valid Flash Command List CMDB 18.3.2.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) Module Base + 0x0009 7 6 5 4 3 2 1 0 0 0 0 0 R FABLO W Reset 0 0 0 0 Figure 18-14. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable. For sector erase, the MCU address bits [8:0] are ignored. For mass erase, any address within the Flash array is valid to start the command. 18.3.2.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-17. RESERVED3 All bits read 0 and are not writable. 18.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-18.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-20. RESERVED6 All bits read 0 and are not writable. 18.4 Functional Description 18.4.1 Flash Command Operations Write operations are used for the program, erase, and erase verify algorithms described in this section.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 18-21. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) START Tbus < 1ms? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[ms]) an integer? yes PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[ms])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ms])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[ms] > 5 AND FCLK > 0.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.4.1.3 Valid Flash Commands Table 18-16 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 18-16. Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 18-22. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Array Address and Dummy Data 2. Write: FCMD register Erase Verify Command 0x05 3.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 18-23. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Address and program Data 2. Write: FCMD register Program Command 0x20 3.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 512 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 18-24. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Sector Address and Dummy Data 2. Write: FCMD register Sector Erase Command 0x40 3.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 18-25. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Block Address and Dummy Data 2. Write: FCMD register Mass Erase Command 0x41 3.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.4.1.4 18.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.4.2 18.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 18.4.5). 18.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
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Chapter 18 32 Kbyte Flash Module (S12FTS32KV1) 18.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 18-1: • FPROT — Flash Protection Register (see Section 18.3.2.5) • FSEC — Flash Security Register (see Section 18.3.2.2) 18.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.1 Introduction The FTS128K1FTS64K module implements a 12864 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 12864 Kbytes organized as 1024512 rows of 128128 bytes with an erase sector size of eight rows (10241024 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.1.3 Modes of Operation See Section 19.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 19.4.1, “Flash Command Operations”. 19.1.4 Block Diagram Figure 19-1Figure 19-2 shows a block diagram of the FTS128K1FTS64K module.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) FTS64K Command Complete Interrupt Flash Interface Command Pipeline Flash Array Command Buffer Empty Interrupt cmd2 addr2 data2 cmd1 addr1 data1 32K * 16 Bits Registers sector 0 sector 1 Protection sector 63 Security Oscillator Clock Clock Divider FCLK Figure 19-2. FTS64K Block Diagram 19.2 External Signal Description The FTS128K1FTS64K module contains no signals that connect off-chip. 19.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) address 0x8000 to 0xBFFF to any physical 16K byte page in the Flash array memory.1 The FPROT register (see Section 19.3.2.5) can be set to globally protect the entire Flash array. Three separate areas, one starting from the Flash array starting address (called lower) towards higher addresses, one growing downward from the Flash array end address (called higher), and the remaining addresses, can be activated for protection.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes 0x5000 0x6000 0x3E Flash Array 0x8000 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B 0x3C 0x3D 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x38–0x3F correspond to the PPAGE register content
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes 0x5000 0x6000 0x3E Flash Array 0x8000 16K PAGED MEMORY 0x3C 0x3D 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x3C–0x3F correspond to the PPAGE register content Figure 19-4.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) Table 19-2. Flash Array Memory Map Summary MCU Address Range PPAGE Protectable Low Range Protectable High Range Array Relative Address(1) 0x0000–0x3FFF(2) Unpaged (0x3D) N.A. N.A. 0x14000–0x17FFF 0x4000–0x7FFF Unpaged (0x3E) 0x4000–0x43FF N.A. 0x18000–0x1BFFF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x38 N.A. N.A. 0x00000–0x03FFF 0x39 N.A. N.A. 0x04000–0x07FFF 0x3A N.A. N.A. 0x08000–0x0BFFF 0x3B N.A. N.A.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) Table 19-3. Flash Array Memory Map Summary MCU Address Range PPAGE Protectable Low Range Protectable High Range Array Relative Address(1) 0x0000–0x3FFF(2) Unpaged (0x3D) N.A. N.A. 0x14000–0x17FFF 0x4000–0x7FFF Unpaged (0x3E) 0x4000–0x43FF N.A. 0x18000–0x1BFFF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x3C N.A. N.A. 0x10000–0x13FFF 0x3D N.A. N.A. 0x14000–0x17FFF 0x3E 0x8000–0x83FF N.A.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 19-5. Detailed descriptions of each register bit are provided.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 R 6 5 4 3 2 1 0 PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 0 0 0 0 0 0 0 FDIVLD W Reset 0 = Unimplemented or Reserved Figure 19-6. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) Table 19-5. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 19-6. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 19-7.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 CBEIE CCIE KEYACC 0 0 0 R 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 19-9. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 19-10. To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) Table 19-10.
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FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPHS[1:0] FPOPEN = 1 Scenario FPLS[1:0] Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) FPHS[1:0] FPOPEN = 0 Scenario FPLS[1:0] 0xFFFF 0xFFFF Protected Flash Figure 19-11. Flash Protection Scenarios 19.3.2.5.1 Flash Protection Restrictions The general guideline is that protection can only be added, not removed.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) Table 19-13. Flash Protection Scenario Transitions To Protection Scenario(1) From Protection Scenario 0 1 6 X 7 X X 1. Allowed transitions marked with X. 19.3.2.6 2 X 3 4 X X X X 5 6 7 X X X X Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) Table 19-14. FSTAT Field Descriptions Field Description 5 PVIOL Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) Table 19-15. FCMD Field Descriptions Field Description 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Valid Flash commands are shown in Table 19-16. An attempt to execute any command other than those listed in Table 19-16 will set the ACCERR bit in the FSTAT register (see Section 19.3.2.6). Table 19-16. Valid Flash Command List CMDB 19.3.2.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) \ Module Base + 0x0008 7 R 6 5 4 3 2 1 0 0 0 0 0 FABHI W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 19-16. Flash Address High Register (FADDRHI) \\ Module Base + 0x0009 7 6 5 4 3 2 1 0 0 0 0 0 R FABLO W Reset 0 0 0 0 Figure 19-17. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 19-20. RESERVED3 All bits read 0 and are not writable. 19.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 19-23. RESERVED6 All bits read 0 and are not writable. 19.4 Functional Description 19.4.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) • • Tbus as the period of the bus clock INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 19-24. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.4.1.3 Valid Flash Commands Table 19-17 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 19-17. Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 19-25. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Array Address and Dummy Data 2. Write: FCMD register Erase Verify Command 0x05 3.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 19-26. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Address and program Data 2. Write: FCMD register Program Command 0x20 3.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 1024 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 19-27. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Sector Address and Dummy Data 2. Write: FCMD register Sector Erase Command 0x40 3.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 19-28. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Block Address and Dummy Data 2. Write: FCMD register Mass Erase Command 0x41 3.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.4.1.4 19.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.4.2 19.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 19.4.5). 19.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 19.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 19-1: • FPROT — Flash Protection Register (see Section 19.3.2.5) • FSEC — Flash Security Register (see Section 19.3.2.2) 19.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted.
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Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) 574 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.1 Introduction The FTS128K1FTS96K module implements a 12896 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 12896 Kbytes organized as 1024768 rows of 128128 bytes with an erase sector size of eight rows (10241024 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.1.3 Modes of Operation See Section 20.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 20.4.1, “Flash Command Operations”. 20.1.4 Block Diagram Figure 20-1Figure 20-2 shows a block diagram of the FTS128K1FTS96K module.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) FTS96K Command Complete Interrupt Flash Interface Command Pipeline Flash Array Command Buffer Empty Interrupt cmd2 addr2 data2 cmd1 addr1 data1 48K * 16 Bits Registers sector 0 sector 1 Protection sector 95 Security Oscillator Clock Clock Divider FCLK Figure 20-2. FTS96K Block Diagram 20.2 External Signal Description The FTS128K1FTS96K module contains no signals that connect off-chip. 20.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) address 0x8000 to 0xBFFF to any physical 16K byte page in the Flash array memory.1 The FPROT register (see Section 20.3.2.5) can be set to globally protect the entire Flash array. Three separate areas, one starting from the Flash array starting address (called lower) towards higher addresses, one growing downward from the Flash array end address (called higher), and the remaining addresses, can be activated for protection.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes 0x5000 0x6000 0x3E Flash Array 0x8000 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B 0x3C 0x3D 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x38–0x3F correspond to the PPAGE register content
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes 0x5000 0x6000 0x3E Flash Array 0x8000 16K PAGED MEMORY 0x3A 0x3B 0x3C 0x3D 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x3A–0x3F correspond to the PPAGE register content Figure 20-4.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Table 20-2. Flash Array Memory Map Summary MCU Address Range PPAGE Protectable Low Range Protectable High Range Array Relative Address(1) 0x0000–0x3FFF(2) Unpaged (0x3D) N.A. N.A. 0x14000–0x17FFF 0x4000–0x7FFF Unpaged (0x3E) 0x4000–0x43FF N.A. 0x18000–0x1BFFF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x38 N.A. N.A. 0x00000–0x03FFF 0x39 N.A. N.A. 0x04000–0x07FFF 0x3A N.A. N.A. 0x08000–0x0BFFF 0x3B N.A. N.A.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Table 20-3. Flash Array Memory Map Summary MCU Address Range PPAGE Protectable Low Range Protectable High Range Array Relative Address(1) 0x0000–0x3FFF(2) Unpaged (0x3D) N.A. N.A. 0x14000–0x17FFF 0x4000–0x7FFF Unpaged (0x3E) 0x4000–0x43FF N.A. 0x18000–0x1BFFF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x3A N.A. N.A. 0x08000–0x0BFFF 0x3B N.A. N.A. 0x0C000–0x0FFFF 0x3C N.A. N.A. 0x10000–0x13FFF 0x3D N.A. N.A.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 20-5. Detailed descriptions of each register bit are provided.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 R 6 5 4 3 2 1 0 PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 0 0 0 0 0 0 0 FDIVLD W Reset 0 = Unimplemented or Reserved Figure 20-6. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Table 20-5. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 20-6. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 20-7.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 CBEIE CCIE KEYACC 0 0 0 R 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 20-9. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 20-10. To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Table 20-10.
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FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPHS[1:0] FPOPEN = 1 Scenario FPLS[1:0] Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) FPHS[1:0] FPOPEN = 0 Scenario FPLS[1:0] 0xFFFF 0xFFFF Protected Flash Figure 20-11. Flash Protection Scenarios 20.3.2.5.1 Flash Protection Restrictions The general guideline is that protection can only be added, not removed.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Table 20-13. Flash Protection Scenario Transitions To Protection Scenario(1) From Protection Scenario 0 1 6 X 7 X X 1. Allowed transitions marked with X. 20.3.2.6 2 X 3 4 X X X X 5 6 7 X X X X Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Table 20-14. FSTAT Field Descriptions Field Description 5 PVIOL Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Table 20-15. FCMD Field Descriptions Field Description 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Valid Flash commands are shown in Table 20-16. An attempt to execute any command other than those listed in Table 20-16 will set the ACCERR bit in the FSTAT register (see Section 20.3.2.6). Table 20-16. Valid Flash Command List CMDB 20.3.2.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Module Base + 0x0009 7 6 5 4 3 2 1 0 0 0 0 0 R FABLO W Reset 0 0 0 0 Figure 20-16. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable. For sector erase, the MCU address bits [9:0] are ignored. For mass erase, any address within the Flash array is valid to start the command. 20.3.2.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 20-19. RESERVED3 All bits read 0 and are not writable. 20.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 20-20.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 20-22. RESERVED6 All bits read 0 and are not writable. 20.4 Functional Description 20.4.1 Flash Command Operations Write operations are used for the program, erase, and erase verify algorithms described in this section.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 20-23. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.4.1.3 Valid Flash Commands Table 20-17 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 20-17. Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 20-24. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Array Address and Dummy Data 2. Write: FCMD register Erase Verify Command 0x05 3.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 20-25. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Address and program Data 2. Write: FCMD register Program Command 0x20 3.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 1024 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 20-26. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Sector Address and Dummy Data 2. Write: FCMD register Sector Erase Command 0x40 3.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 20-27. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Block Address and Dummy Data 2. Write: FCMD register Mass Erase Command 0x41 3.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.4.1.4 20.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.4.2 20.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 20.4.5). 20.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 20.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 20-1: • FPROT — Flash Protection Register (see Section 20.3.2.5) • FSEC — Flash Security Register (see Section 20.3.2.2) 20.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted.
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Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) 612 MC9S12C-Family / MC9S12GC-Family Rev 01.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.1 Introduction The FTS128K1 module implements a 128 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 128 Kbytes organized as 1024 rows of 128 bytes with an erase sector size of eight rows (1024 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.1.3 Modes of Operation See Section 21.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 21.4.1, “Flash Command Operations”. 21.1.4 Block Diagram Figure 21-1 shows a block diagram of the FTS128K1 module.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.3 Memory Map and Registers This section describes the FTS128K1 memory map and registers. 21.3.1 Module Memory Map The FTS128K1 memory map is shown in Figure 21-2. The HCS12 architecture places the Flash array addresses between 0x4000 and 0xFFFF, which corresponds to three 16 Kbyte pages.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes 0x5000 0x6000 0x3E Flash Array 0x8000 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B 0x3C 0x3D 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x38–0x3F correspond to the PPAGE register conten
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) Table 21-2. Flash Array Memory Map Summary MCU Address Range PPAGE Protectable Low Range Protectable High Range Array Relative Address(1) 0x0000–0x3FFF(2) Unpaged (0x3D) N.A. N.A. 0x14000–0x17FFF 0x4000–0x7FFF Unpaged (0x3E) 0x4000–0x43FF N.A. 0x18000–0x1BFFF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x38 N.A. N.A. 0x00000–0x03FFF 0x39 N.A. N.A. 0x04000–0x07FFF 0x3A N.A. N.A. 0x08000–0x0BFFF 0x3B N.A. N.A.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 21-3. Detailed descriptions of each register bit are provided.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 R 6 5 4 3 2 1 0 PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 0 0 0 0 0 0 0 FDIVLD W Reset 0 = Unimplemented or Reserved Figure 21-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) Table 21-4. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 21-5. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 21-6.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 CBEIE CCIE KEYACC 0 0 0 R 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 21-7. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 21-8. To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) Table 21-9.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPHS[1:0] FPOPEN = 1 Scenario FPLS[1:0] FPHDIS = 1 FPLDIS = 1 FPHS[1:0] FPOPEN = 0 Scenario FPLS[1:0] 0xFFFF 0xFFFF Protected Flash Figure 21-9. Flash Protection Scenarios 21.3.2.5.1 Flash Protection Restrictions The general guideline is that protection can only be added, not removed.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) Table 21-12. Flash Protection Scenario Transitions To Protection Scenario(1) From Protection Scenario 0 1 6 X 7 X X 1. Allowed transitions marked with X. 21.3.2.6 2 X 3 4 X X X X 5 6 7 X X X X Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) Table 21-13. FSTAT Field Descriptions Field Description 5 PVIOL Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) Table 21-14. FCMD Field Descriptions Field Description 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Valid Flash commands are shown in Table 21-15. An attempt to execute any command other than those listed in Table 21-15 will set the ACCERR bit in the FSTAT register (see Section 21.3.2.6). Table 21-15. Valid Flash Command List CMDB 21.3.2.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) Module Base + 0x0009 7 6 5 4 3 2 1 0 0 0 0 0 R FABLO W Reset 0 0 0 0 Figure 21-14. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable. For sector erase, the MCU address bits [9:0] are ignored. For mass erase, any address within the Flash array is valid to start the command. 21.3.2.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 21-17. RESERVED3 All bits read 0 and are not writable. 21.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 21-18.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 21-20. RESERVED6 All bits read 0 and are not writable. 21.4 Functional Description 21.4.1 Flash Command Operations Write operations are used for the program, erase, and erase verify algorithms described in this section.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 21-21. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.4.1.3 Valid Flash Commands Table 21-16 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 21-16. Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 21-22. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Array Address and Dummy Data 2. Write: FCMD register Erase Verify Command 0x05 3.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 21-23. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Address and program Data 2. Write: FCMD register Program Command 0x20 3.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 1024 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 21-24. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Sector Address and Dummy Data 2. Write: FCMD register Sector Erase Command 0x40 3.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 21-25. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Block Address and Dummy Data 2. Write: FCMD register Mass Erase Command 0x41 3.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.4.1.4 21.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.4.2 21.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 21.4.5). 21.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
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Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1) 21.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 21-1: • FPROT — Flash Protection Register (see Section 21.3.2.5) • FSEC — Flash Security Register (see Section 21.3.2.2) 21.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted.
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Appendix A Electrical Characteristics Appendix A Electrical Characteristics A.1 General NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. The parts are specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.
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Appendix A Electrical Characteristics VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic. VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE In the following context VDD5 is used for either VDDA, VDDR, and VDDX; VSS5 is used for either VSSA, VSSR, and VSSX unless otherwise noted.
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Appendix A Electrical Characteristics injection current may flow out of VDD5 and could result in external power supply going out of regulation. Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only.
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Appendix A Electrical Characteristics A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification.
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Appendix A Electrical Characteristics A.1.7 Operating Conditions This chapter describes the operating conditions of the devices. Unless otherwise noted those conditions apply to all the following data. NOTE Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” . Table A-4.
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Appendix A Electrical Characteristics A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded.
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Appendix A Electrical Characteristics Table A-5.
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Appendix A Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. Table A-6. 5V I/O Characteristics Conditions are 4.5< VDDX <5.5V Temperature from –40˚C to +140˚C, unless otherwise noted Num C 1 2 3 Rating Symbol Min Typ Max Unit 0.65*VDD5 — — V P Input High Voltage V T Input High Voltage VIH — — VDD5 + 0.
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Appendix A Electrical Characteristics Table A-7. 3.3V I/O Characteristics Conditions are VDDX=3.3V +/-10%, Temperature from –40˚C to +140˚C, unless otherwise noted Num C 1 2 3 Rating Symbol Min Typ Max Unit 0.65*VDD5 — — V P Input High Voltage V T Input High Voltage VIH — — VDD5 + 0.3 V P Input Low Voltage VIL — — 0.35*VDD5 V T Input Low Voltage VIL VSS5 – 0.
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Appendix A Electrical Characteristics A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-8.
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Appendix A Electrical Characteristics Table A-9. Supply Current Characteristics for Other Family Members Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted Num C 1 P Rating Run Supply Current Single Chip, Symbol Min Typ Max Unit IDD5 — — 45 mA — — — — 2.5 3.5 33 8 — — — — — — — — — 190 200 300 400 450 600 650 1000 — 250 — 1400 — 1900 — 4800 — — — — — 370 500 590 780 1200 — — — — — Wait Supply current 2 All modules enabled VDDR<4.
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Appendix A Electrical Characteristics A.2 ATD Characteristics This section describes the characteristics of the analog-to-digital converter. VRL is not available as a separate pin in the 48- and 52-pin versions. In this case the internal VRL pad is bonded to the VSSA pin. The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test. A.2.
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Appendix A Electrical Characteristics A.2.2 ATD Operating Characteristics In 3.3V Range The Table A-11 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped Table A-11.
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Appendix A Electrical Characteristics A.2.3.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive conditions. 2. Current is injected into pins in the neighborhood of the channel being converted.
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Appendix A Electrical Characteristics A.2.5 ATD Accuracy (3.3V Range) Table A-13 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-13. ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV fATDCLK = 2.0MHz Num C 1 P 2 3 Rating Symbol Min Typ Max Unit 10-Bit Resolution LSB — 3.
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Appendix A Electrical Characteristics DNL Vi-1 $3FF LSB 10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary $3FE $3FD $3FC $FF $3FB $3FA $3F9 $3F8 $FE $3F7 $3F6 $3F5 $FD 10-Bit Resolution $3F3 9 Ideal Transfer Curve 8 2 8-Bit Resolution $3F4 7 10-Bit Transfer Curve 6 5 4 1 3 8-Bit Transfer Curve 2 1 0 3.25 6.5 9.75 13 16.25 19.5 22.75 26 29.25 3286 3289 3292 3295 3299 3302 3305 3309 3312 3315 3318 3321 3324 3328 Vin mV Figure A-1.
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Appendix A Electrical Characteristics A.3 MSCAN Table A-14. MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P MSCAN Wake-up dominant pulse filtered tWUP — — 2 us 2 P MSCAN Wake-up dominant pulse pass tWUP 5 — — us A.4 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). A.4.
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Appendix A Electrical Characteristics A.4.1.3 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set. A.4.1.
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Appendix A Electrical Characteristics Table A-16. Oscillator Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1a C Rating Crystal oscillator range (Colpitts) (1) 4 Symbol Min Typ Max Unit fOSC 0.5 — 16 MHz fOSC 0.5 — 40 MHz iOSC 100 — — µA 1b C Crystal oscillator range (Pierce) 2 P Startup Current 3 C Oscillator start-up time (Colpitts) tUPOSC — 8(2) 100(3) ms 4 D Clock Quality check time-out tCQOUT 0.45 — 2.
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Appendix A Electrical Characteristics A.4.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.4.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Cp VDDPLL R Cs XFC Pin Phase fosc 1 fref D refdv+1 VCO fvco KF fcmp KV Detector Loop Divider 1 synr+1 1 2 Figure A-2.
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Appendix A Electrical Characteristics The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10, typical values are 50. ζ = 0.9 ensures a good transient response. f ref 2 ⋅ ζ ⋅ f ref 1 f C < ------------------------------------------ ⋅ ----- → f C < ------------- ;( ζ = 0.
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Appendix A Electrical Characteristics 1 0 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Figure A-3. Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N).
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Appendix A Electrical Characteristics Table A-17. PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Self Clock Mode frequency fSCM 1 — 5.5 MHz 2 D VCO locking range fVCO 8 — 50 MHz 3 D |∆trk| 3 — 4 %(1) 4 D Lock Detection |∆Lock| 0 — 1.5 %1 5 D Un-Lock Detection |∆unl| 0.5 — 2.5 %1 6 D |∆unt| 6 — 8 %1 7 C PLLON Total Stabilization delay (Auto Mode) (2) tstab — 0.5 — ms tacq — 0.
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Appendix A Electrical Characteristics A.5.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency f¨NVMOP and can be calculated according to the following formula. 1 1 t swpgm = 9 ⋅ --------------------- + 25 ⋅ ---------f NVMOP f bus A.5.1.
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Appendix A Electrical Characteristics Table A-18. NVM Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 D 2 Symbol Min Typ Max Unit External Oscillator Clock fNVMOSC 0.5 — 50(1) MHz D Bus frequency for Programming or Erase Operations fNVMBUS 1 — 3 D Operating Frequency fNVMOP 150 — 200 kHz 4 P Single Word Programming Time tswpgm 46(2) — 74.5(3) µs tbwpgm 2 5 D Rating Flash Burst Programming consecutive word 20.
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Appendix A Electrical Characteristics A.5.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Table A-19. NVM Reliability Characteristics(1) Conditions are shown in Table A-4.
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Appendix A Electrical Characteristics Figure A-5. Typical Endurance vs Temperature 500 Typical Endurance [103 Cycles] 450 400 350 300 250 200 150 100 50 0 -40 -20 0 20 40 60 80 100 120 140 Operating Temperature TJ [°C] ------ Flash A.6 SPI This section provides electrical parametrics and ratings for the SPI. In Table A-20 the measurement conditions are listed. Table A-20.
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Appendix A Electrical Characteristics SS1 (OUTPUT) 2 1 SCK (CPOL = 0) (OUTPUT) 12 13 12 13 3 4 4 SCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN2 BIT 6 . . . 1 10 MOSI (OUTPUT) LSB IN 9 MSB OUT2 11 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-6. SPI Master Timing (CPHA=0) In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
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Appendix A Electrical Characteristics In Table A-21 the timing characteristics for master mode are listed. Table A-21.
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Appendix A Electrical Characteristics In Figure A-9 the timing diagram for slave mode with transmission format CPHA=1 is depicted. SS (INPUT) 3 1 2 12 13 12 13 SCK (CPOL = 0) (INPUT) 4 4 SCK (CPOL = 1) (INPUT) MISO (OUTPUT) see note 7 SLAVE MSB OUT 5 MOSI (INPUT) 8 11 9 BIT 6 . . . 1 SLAVE LSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined! Figure A-9. SPI Slave Timing (CPHA=1) In Table A-22 the timing characteristics for slave mode are listed. Table A-22.
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Appendix A Electrical Characteristics A.7 Voltage Regulator A.7.1 Voltage Regulator Operating Conditions Table A-23. Voltage Regulator Electrical Parameters Num C Characteristic Symbol Min Typ Max Unit 1 P Input Voltages VVDDR, A 2.97 — 5.5 V 3 P Output Voltage Core Full Performance Mode VDD 2.35 2.5 2.
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Appendix A Electrical Characteristics V VDDA VLVID VLVIA VDD VLVRD VLVRA VPORD t LVI LVI enabled LVI disabled due to LVR POR LVR Figure A-10. Voltage Regulator — Chip Power-up and Voltage Drops (not scaled) A.7.3 A.7.3.1 Output Loads Resistive Loads The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads. A.7.3.2 Capacitive Loads The capacitive loads are specified in Table A-24.
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Appendix B Emulation Information Appendix B Emulation Information B.
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Appendix B Emulation Information B.1.1 PK[2:0] / XADDR[16:14] PK2-PK0 provide the expanded address XADDR[16:14] for the external bus. Refer to the S12 Core user guide for detailed information about external address page access. Pin Name Function 1 PK[2:0] Pin Name Function 2 XADDR[16:14] Internal Pull Resistor Power Domain VDDX Description CTRL Reset State PUPKE Up Port K I/O Pins The reset state of DDRK in the S12_CORE is $00, configuring the pins as inputs.
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Appendix C Package Information Appendix C Package Information C.1 General This section provides the physical dimensions of the packages 48LQFP, 52LQFP, 80QFP. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.
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Appendix C Package Information C.1.1 80-Pin QFP Package L 60 41 61 D S M V P B C A-B D 0.20 M B B -A-,-B-,-D- 0.20 L H A-B -B- 0.05 D -A- S S S 40 DETAIL A DETAIL A 21 80 1 0.20 A H A-B M S F 20 -DD S 0.05 A-B J S 0.20 C A-B M S D S D M E DETAIL C C -H- -C- DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.10 H SEATING PLANE N M G U T DATUM PLANE -H- R K W X DETAIL C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.
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Appendix C Package Information C.1.2 52-Pin LQFP Package 4X 4X 13 TIPS 0.20 (0.008) H L-M N 0.20 (0.008) T L-M N -XX=L, M, N 52 40 1 CL 39 AB 3X G VIEW Y -L- -M- AB B B1 13 V VIEW Y BASE METAL F PLATING V1 27 14 J 26 U -N- A1 0.13 (0.005) M D T L-M S N S S1 SECTION AB-AB A ROTATED 90 ° CLOCKWISE S 4X C θ2 0.10 (0.004) T -H-TSEATING PLANE 4X θ3 VIEW AA 0.05 (0.002) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
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Appendix C Package Information C.1.3 48-Pin LQFP Package 4X 0.200 AB T-U Z DETAIL Y A P A1 48 37 1 36 T U B V AE B1 12 25 13 AE V1 24 DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA Z S1 T, U, Z S DETAIL Y 4X 0.200 AC T-U Z 0.080 AC G AB AD AC MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 ° 7° 12 ° REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.
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Appendix D Derivative Differences Appendix D Derivative Differences The Device User Guide provides information about the MC9S12C-Family and the MC9S12GC-Family. The C-Family and the GC-Family offer an extensive range of package, temperature and speed options. The members of the GC-Family are a subset of the C-family that do not feature a CAN module. Table D-1. shows a feature overview of the C and GC family members. Table D-1.
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Appendix E Ordering Information Appendix E Ordering Information MC9S12 C32 C FU(E) 25 Speed Option Environment Option Package Option Temperature Option Device Title Controller Family Temperature Options C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C Package Options FU = 80QFP PB = 52LQFP FA = 48LQFP Speed Options 25 = 25MHz bus 16 = 16MHz bus Environment Option E = Environmentally Preferred Package Figure E-1. Order Part number Coding Table E-1.
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Appendix E Ordering Information Part Number Mask(1) set Temp.
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Appendix E Ordering Information Part Number Mask(1) set Temp.
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How to Reach Us: Home Page: www.freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 1-800-521-6274 or 480-768-2130 Europe, Middle East, and Africa: +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) Japan: Freescale Semiconductor Japan Ltd.