Datasheet

Chapter 3 Module Mapping Control (MMCV4) Block Description
Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 119
Rev 01.24
NOTE
As stated, the bits in this register provide read visibility to the system
physical memory space allocations defined at system integration. The actual
array size for any given type of memory block may differ from the allocated
size. Please refer to the device overview chapter for actual sizes.
3.3.2.8 Memory Size Register 1 (MEMSIZ1)
Read: Anytime
Write: Writes have no effect
Reset: Defined at chip integration, see device overview section.
The MEMSIZ1 register reflects the state of the FLASH or ROM physical memory space and paging
switches at the core boundary which are configured at system integration. This register allows read
visibility to the state of these switches.
011 8K bytes 8K bytes RAM[15:13] 0x0000
100 10K bytes 16K bytes
2
RAM[15:14] 0x1800
101 12K bytes 16K bytes
2
RAM[15:14] 0x1000
110 14K bytes 16K bytes
2
RAM[15:14] 0x0800
111 16K bytes 16K bytes RAM[15:14] 0x0000
1. The RAM Reset BASE Address is based on the reset value of the INITRM register, 0x0009.
2. Alignment of the Allocated RAM space within the RAM mappable region is dependent on the value of RAMHAL.
Module Base + 0x001D
Starting address location affected by INITRG register setting.
76543210
R ROM_SW1 ROM_SW0 0 0 0 0 PAG_SW1 PAG_SW0
W
Reset — — ——————
= Unimplemented or Reserved
Figure 3-10. Memory Size Register 1 (MEMSIZ1)
Table 3-9. Allocated RAM Memory Space (continued)
ram_sw2:ram_sw0
Allocated
RAM Space
RAM
Mappable Region
INITRM
Bits Used
RAM Reset
Base Address
(1)