Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Operating Modes
MC9S12DP256 — Revision 1.1
Operating Modes
Special Operating
Modes
There are two special operating modes that correspond to normal
operating modes. These operating modes are commonly used in factory
testing and system development.
Special Single-Chip Mode — When the MCU is reset in this
mode, the background debug mode is enabled and “active”. The
MCU does not fetch the reset vector and execute application code
as it would in other modes. Instead the active background mode is
in control of CPU execution and BDM firmware is waiting for
additional serial commands through the BKGD pin. When a serial
command instructs the MCU to return to normal execution, the
system will be configured as described below unless the reset
states of internal control registers have been changed through
background commands after the MCU was reset.
There is no external expansion bus after reset in this mode. Ports
A and B are initially simple bidirectional I/O pins that are
configured as high-impedance inputs with internal pullups
disabled; however, writing to the mode select bits in the MODE
register (which is allowed in special modes) can change this after
reset. All of the Port E pins (except PE4/ECLK) are initially
configured as general purpose high-impedance inputs with
pullups enabled. PE4/ECLK is configured as the E clock output in
this mode.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be
configured for their alternate functions IPIPE1, IPIPE0, LSTRB
,
and R/W
while the MCU is in single chip modes. In single chip
modes, the associated control bits PIPOE, LSTRE and RDWE are
reset to zero. Writing the opposite value into these bits in single
chip mode does not change the operation of the associated Port
E pins.
Port E, bit 4 can be configured for a free-running E clock output by
clearing NECLK=0. Typically the only use for an E clock output
while the MCU is in single chip modes would be to get a constant
speed clock for use in the external application system.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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