Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Operating Modes
Operating Modes
MC9S12DP256 — Revision 1.1
Operating Modes
Emulation Expanded Narrow Mode — Expanded narrow modes
are intended to allow connection of single 8-bit external memory
devices for lower cost systems that do not need the performance
of a full 16-bit external data bus. Accesses to internal resources
that have been mapped external (i.e. PORTA, PORTB, DDRA,
DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed
with a 16-bit data bus on Ports A and B. Accesses of 16-bit
external words to addresses which are normally mapped external
will be broken into two separate 8-bit accesses using Port A as an
8-bit data bus. Internal operations continue to use full 16-bit data
paths. They are only visible externally as 16-bit information if
IVIS=1.
Ports A and B are configured as multiplexed address and data
output ports. During external accesses, address A15, data D15
and D7 are associated with PA7, address A0 is associated with
PB0 and data D8 and D0 are associated with PA0. During internal
visible accesses and accesses to internal resources that have
been mapped external, address A15 and data D15 is associated
with PA7 and address A0 and data D0 is associated with PB0.
The bus control related pins in Port E (PE7/NOACC,
PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK,
PE3/LSTRB
/TAGLO, and PE2/R/W) are all configured to serve
their bus control output functions rather than general purpose I/O.
Notice that writes to the bus control enable bits in the PEAR
register in special mode are restricted.
The main difference between special modes and normal modes is
that some of the bus control and system control signals cannot be
written in special modes.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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