Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Operating Modes
MC9S12DP256 — Revision 1.1
Operating Modes
any attempt to write to an external location. If there are no writable
resources in the external system, PE2 can be left as a general
purpose I/O pin.
Internal Visibility — Internal visibility is available when the MCU
is operating in expanded wide modes or special narrow mode. It is
not available in single-chip, peripheral or normal expanded narrow
modes. Internal visibility is enabled by setting the IVIS bit in the
MODE register.
If an internal access is made while E, R/W
, and LSTRB are
configured as bus control outputs and internal visibility is off
(IVIS=0), E will remain low for the cycle, R/W
will remain high, and
address, data and the LSTRB
pins will remain at their previous
state.
When internal visibility is enabled (IVIS=1), certain internal cycles
will be blocked from going external. During cycles when the BDM
is selected, R/W
will remain high, data will maintain its previous
state, and address and LSTRB
pins will be updated with the
internal value. During CPU no access cycles when the BDM is not
driving, R/W
will remain high, and address, data and the LSTRB
pins will remain at their previous state.
Emulation Expanded Wide Mode — In expanded wide modes,
Ports A and B are configured as a 16-bit multiplexed address and
data bus and Port E provides bus control and status signals.
These signals allow external memory and peripheral devices to be
interfaced to the MCU. These signals can also be used by a logic
analyzer to monitor the progress of application programs.
The bus control related pins in Port E (PE7/NOACC,
PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK,
PE3/LSTRB
/TAGLO, and PE2/R/W) are all configured to serve
their bus control output functions rather than general purpose I/O.
Notice that writes to the bus control enable bits in the PEAR
register in special mode are restricted.
The main difference between special modes and normal modes is
that some of the bus control and system control signals cannot be
written in special modes.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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