Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Operating Modes
Operating Modes
MC9S12DP256 — Revision 1.1
Operating Modes
Normal Expanded Narrow Mode — This mode is used for lower
cost production systems that use 8-bit wide external EPROMs or
RAMs. Such systems take extra bus cycles to access 16-bit
locations but this may be preferred over the extra cost of additional
external memory devices.
Ports A and B are configured as a 16-bit address bus and Port A
is multiplexed with data. Internal visibility is not available in this
mode because the internal cycles would need to be split into two
8-bit cycles.
Since the PEAR register can only be written one time in this mode,
use care to set all bits to the desired states during the single
allowed write.
The PE3/LSTRB
pin is always a general purpose I/O pin in normal
expanded narrow mode. Although it is possible to write the LSTRE
bit in PEAR to “1” in this mode, the state of LSTRE is overridden
and Port E bit 3 cannot be reconfigured as the LSTRB
output.
It is possible to enable the pipe status signals on Port E bits 6 and
5 by setting the PIPOE bit in PEAR, but it would be unusual to do
so in this mode. LSTRB
would also be needed to fully understand
system activity. Development systems where pipe status signals
are monitored would typically use special expanded wide mode or
occasionally special expanded narrow mode.
The PE4/ECLK pin is initially configured as ECLK output with
stretch. The E clock output function depends upon the settings of
the NECLK bit in the PEAR register, the IVIS bit in the MODE
register and the ESTR bit in the EBICTL register. In normal
expanded narrow mode, the E clock is available for use in external
select decode logic or as a constant speed clock for use in the
external application system.
The PE2/R/W
pin is initially configured as a general purpose input
with a pullup but this pin can be reconfigured as the R/W
bus
control signal by writing “1” to the RDWE bit in PEAR. If the
expanded narrow system includes external devices that can be
written such as RAM, the RDWE bit would need to be set before
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