Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Operating Modes
MC9S12DP256 — Revision 1.1
Operating Modes
Normal Expanded Wide Mode — In expanded wide modes,
Ports A and B are configured as a 16-bit multiplexed address and
data bus and Port E bit 4 is configured as the E clock output signal.
These signals allow external memory and peripheral devices to be
interfaced to the MCU.
Port E pins other than PE4/ECLK are configured as general
purpose I/O pins (initially high-impedance inputs with internal
pullup resistors enabled). Control bits PIPOE, NECLK, LSTRE,
and RDWE in the PEAR register can be used to configure Port E
pins to act as bus control outputs instead of general purpose I/O
pins.
It is possible to enable the pipe status signals on Port E bits 6 and
5 by setting the PIPOE bit in PEAR, but it would be unusual to do
so in this mode. Development systems where pipe status signals
are monitored would typically use the special variation of this
mode.
The Port E bit 2 pin can be reconfigured as the R/W
bus control
signal by writing “1” to the RDWE bit in PEAR. If the expanded
system includes external devices that can be written, such as
RAM, the RDWE bit would need to be set before any attempt to
write to an external location. If there are no writable resources in
the external system, PE2 can be left as a general purpose I/O pin.
The Port E bit 3 pin can be reconfigured as the LSTRB
bus control
signal by writing “1” to the LSTRE bit in PEAR. The default
condition of this pin is a general purpose input because the
LSTRB
function is not needed in all expanded wide applications.
The Port E bit 4 pin is initially configured as ECLK output with
stretch. The E clock output function depends upon the settings of
the NECLK bit in the PEAR register, the IVIS bit in the MODE
register and the ESTR bit in the EBICTL register. The E clock is
available for use in external select decode logic or as a constant
speed clock for use in the external application system.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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