Datasheet

Operating Modes
Operating Modes
MC9S12DP256 — Revision 1.1
Operating Modes
PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs
during reset.
The following paragraphs discuss the default bus setup and describe
which aspects of the bus can be changed after reset on a per mode
basis.
Normal Operating
Modes
These modes provide three operating configurations. Background
debug is available in all three modes, but must first be enabled for some
operations by means of a BDM background command, then activated.
Normal Single-Chip Mode — There is no external expansion bus
in this mode. All pins of Ports A, B and E are configured as general
purpose I/O pins Port E bits 1 and 0 are available as general
purpose input only pins with internal pullups enabled. All other
pins of Port E are bidirectional I/O pins that are initially configured
as high-impedance inputs with internal pullups enabled. Ports A
and B are configured as high-impedance inputs with their internal
pullups disabled.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be
configured for their alternate functions IPIPE1, IPIPE0, LSTRB
,
and R/W
while the MCU is in single chip modes. In single chip
modes, the associated control bits PIPOE, LSTRE, and RDWE
are reset to zero. Writing the opposite state into them in single chip
mode does not change the operation of the associated Port E
pins.
In normal single chip mode, the MODE register is writable one
time. This allows a user program to change the bus mode to
special single chip or narrow or wide expanded mode and/or turn
on visibility of internal accesses.
Port E, bit 4 can be configured for a free-running E clock output by
clearing NECLK=0. Typically the only use for an E clock output
while the MCU is in single chip modes would be to get a constant
speed clock for use in the external application system.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...