Datasheet

Operating Modes
MC9S12DP256 — Revision 1.1
Operating Modes
There are two basic types of operating modes:
Normal
modes — some registers and bits are protected
against accidental changes.
Special
modes — allow greater access to protected control
registers and bits for special purposes such as testing.
A system development and debug feature, background debug mode
(BDM), is available in all modes. In special single-chip mode, BDM is
active immediately after reset.
Some aspects of Port E are not mode dependent. Bit 1 of Port E is a
general purpose input or the IRQ
interrupt input. IRQ can be enabled by
bits in the CPUs condition codes register but it is inhibited at reset so this
pin is initially configured as a simple input with a pullup. Bit 0 of Port E is
a general purpose input or the XIRQ
interrupt input. XIRQ can be
enabled by bits in the CPUs condition codes register but it is inhibited at
reset so this pin is initially configured as a simple input with a pullup. The
ESTR bit in the EBICTL register is set to one by reset in any user mode.
This assures that the reset vector can be fetched even if it is located in
an external slow memory device. The PE6/MODB/IPIPE1 and
Table 13 Mode Selection
Input
BKGD
& bit
MODC
Input
& bit
MODB
Input
& bit
MODA
Mode Description
000
Special Single Chip, BDM allowed and ACTIVE. BDM is “allowed” in all
other modes but a serial command is required to make BDM “active”.
0 0 1 Emulation Expanded Narrow, BDM allowed
0 1 0 Special Test (Expanded Wide), BDM allowed
0 1 1 Emulation Expanded Wide, BDM allowed
1 0 0 Normal Single Chip, BDM allowed
1 0 1 Normal Expanded Narrow, BDM allowed
110
Peripheral; BDM allowed but bus operations would cause bus conflicts
(must not be used)
1 1 1 Normal Expanded Wide, BDM allowed
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...