Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Glossary
MC9S12DP256 — Revision 1.1
Glossary
stop bit — A bit that signals the end of an asynchronous serial
transmission.
subroutine — A sequence of instructions to be used more than once in
the course of a program. The last instruction in a subroutine is a
return from subroutine (RTS) instruction. At each place in the
main program where the subroutine instructions are needed, a
jump or branch to subroutine (JSR or BSR) instruction is used to
call the subroutine. The CPU leaves the flow of the main program
to execute the instructions in the subroutine. When the RTS
instruction is executed, the CPU returns to the main program
where it left off.
synchronous — Refers to logic circuits and operations that are
synchronized by a common reference signal.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or
from a logic 1 to a logic 0.
tracking mode — A mode of PLL operation with narrow loop bandwidth.
Also see ‘acquisition mode.’
two’s complement — A means of performing binary subtraction using
addition techniques. The most significant bit of a two’s
complement number indicates the sign of the number (1 indicates
negative). The two’s complement negative of a number is
obtained by inverting each bit in the number and then adding 1 to
the result.
unbuffered — Utilizes only one register for data; new data overwrites
current data.
unimplemented memory location — A memory location that is not
used. Writing to an unimplemented location has no effect.
Reading an unimplemented location returns an unpredictable
value.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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