Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Glossary
MC9S12DP256 — Revision 1.1
Glossary
overflow — A quantity that is too large to be contained in one byte or
one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s
in each byte transmitted. In a system that uses odd parity, every
byte is expected to have an odd number of logic 1s. In an even
parity system, every byte should have an even number of logic
1s. In the transmitter, a parity generator appends an extra bit to
each byte to make the number of logic 1s odd for odd parity or
even for even parity. A parity checker in the receiver counts the
number of logic 1s in each byte. The parity checker generates an
error signal if it finds a byte with an incorrect number of logic 1s.
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A clock generator circuit in which a voltage
controlled oscillator produces an oscillation which is
synchronized to a reference signal.
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a
pointer register because its contents are used in the calculation
of the address of an operand, and therefore points to the operand.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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