Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

MC9S12DP256 — Revision 1.1
Revision History
Revision History
Revision History
This section lists the revision history of the document since Rev 1.0 (the
first general release). Data for previous revisions is unavailable.
Changes from Rev 1.0 to Rev 1.1
Section Page (in Rev 1.1) Description of change
General Description various Notes about 80-pin version of device added
Pinout and Signal
Description
various Notes about 80-pin version of device added
Pinout and Signal
Description
54
Table 7:
Pin 46 corrected from XTAL to EXTAL
Pinout and Signal
Description
54
Table 7:
Pin 47 corrected from EXTAL to XTAL
Pinout and Signal
Description
55
Table 7:
Pin 68 corrected from PAD10/AN08 to PAD08/AN08
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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