Datasheet

Breakpoint (BKP) Module
MC9S12DP256 — Revision 1.1
Breakpoint (BKP) Module
Breakpoint Operating Modes
Dual Address
Mode
When Dual Address Mode is enabled, two address breakpoints can be
set. Each breakpoint can cause a software interrupt (SWI) or cause the
part to enter BDM. The BDM requests have a higher priority than the
SWI requests. No data breakpoints are allowed.
The BKTAG bit in the BKPCT0 register selects whether the breakpoint
mode is force or tag. The BKxMBH:L bits in the BKPCT1 register select
whether or not the breakpoint is matched exactly or is a range
breakpoint. They also select whether the address is matched on the high
byte, low byte, both bytes, and/or memory expansion. The BKxRW and
BKxRWE bits in the BKPCT1 register select whether the type of bus
cycle to match is a read, write, or both when performing forced
breakpoints.
Full Breakpoint
Mode
When in Full Breakpoint Mode, the part enters background debug mode
or initiates a software interrupt. The BDM requests have a higher priority
than the SWI requests. This mode requires a match on address and data
for a breakpoint to occur. R/W matches are also allowed.
The BKTAG bit in the BKPCT0 register selects whether the breakpoint
mode is forced or tagged. If the BKTAG bit is set in BKPCT0, then only
address is matched, data is ignored. The BK0MBH:L bits in the BKPCT1
register select whether or not the breakpoint is matched exactly, is a
range breakpoint, or is in page space. The BK1MBH:L bits in the
BKPCT1 register select whether the data is matched on the high byte,
low byte, or both bytes. The BK0RW and BK0RWE bits in the BKPCT1
register select whether the type of bus cycle to match is a read or a write
when performing forced breakpoints. BK1RW and BK1RWE bits in the
BKPCT1 register are not used in Full Mode.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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